What is parasitic extraction, and why is it redone after routing?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Parasitic extraction calculates the resistance and capacitance of every routed net from its real geometry. Those values, usually written as SPEF, feed timing and signal integrity analysis. Before routing they are estimates; after routing they come from actual wire length, width, layers, vias and neighbours, so they have to be recalculated.
Technical Explanation
- Every wire has resistance along its length and capacitance to everything around it. Delay depends on both, so timing needs them per net.
- Capacitance has three main parts. Area capacitance is between the bottom and top faces of the wire and the layers above and below. Fringe capacitance comes from the wire's edges to surfaces around it. Sidewall capacitance is between the side of one wire and the side of its neighbour on the same layer.
- Sidewall capacitance grows as wires get taller and closer together, which is why it matters more at advanced nodes. It is also the coupling capacitance that causes crosstalk.
- Resistance depends on length, width, thickness and material, plus every via along the way. Foundries provide sheet resistance and capacitance coefficients measured on test silicon for each process corner.
- Before routing, the tools estimate parasitics from virtual routes or global routes. After routing, the real shapes include detours, layer changes and specific neighbours that no estimate captured.
- The result is normally written as SPEF (Standard Parasitic Exchange Format), with each net's resistors, capacitors to ground and coupling capacitors to other nets. Signoff timing reads that file.
- Extraction is repeated in every RC corner, because metal thickness and width vary. A net can be worst for resistance in one corner and worst for capacitance in another.
- Extraction style should match its use. A lumped capacitance number is enough for dynamic power analysis, but timing and signal integrity need a distributed RC network with coupling capacitors kept separate, because resistance shields some of the far capacitance from the driver and coupling depends on what the neighbour is doing.
Common Mistake
The Trap: Comparing preroute timing to signoff timing and assuming the difference is a tool bug. The preroute number used estimated parasitics; signoff used extraction on real metal in a specific RC corner. The right move is to compare the two runs net by net to see which nets gained capacitance, and to check correlation between tools on the same parasitics.
Follow-up Question & Model Response
"Why does sidewall capacitance matter more than area capacitance at advanced nodes?"
Candidate Model Response: Wires have become taller relative to their width, and the spacing between neighbours has shrunk. Sidewall capacitance is proportional to the facing height and inversely proportional to spacing, so both trends increase it. Area capacitance depends on width and the distance to the layer below, which have not shrunk the same way. As a result, most of a narrow wire's capacitance can be to its neighbours, which also means most of it can switch, causing crosstalk.
Practical Example
Tapeout Scenario: A 250 um M3 net has an estimated 21 fF before routing (illustrative). After routing it detours 30 um around a blockage and runs 180 um next to another M3 net. Extraction reports 29 fF: 9 fF area, 6 fF fringe and 14 fF sidewall, of which 11 fF is coupling to that one neighbour. Timing on the new value adds 6 ps to the path, and with signal integrity analysis enabled, crosstalk adds up to another 4 ps when the neighbour switches the opposite way. The same net in the RCworst corner, with thinner metal, extracts at 1.3 times the resistance of the typical corner, so its delay moves again. Signoff therefore extracts every corner separately and checks timing against each one.
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