What are RC extraction corners (Cworst, Cbest, RCworst, RCbest), and why do you need several?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
RC corners describe how manufacturing variation in metal width and thickness changes wire resistance and capacitance. Because the same variation pushes resistance and capacitance in opposite directions, no single corner is worst for every path. Cworst maximizes capacitance, RCworst maximizes the resistance-capacitance product, and the best corners are their opposites, used mainly for hold.
Technical Explanation
- Metal width varies with etch and thickness varies with polishing. A wider or thicker wire has lower resistance but more capacitance; a narrower or thinner wire has higher resistance but less capacitance.
- Cworst, sometimes written Cmax, picks the variation that gives the highest capacitance. In a typical corner definition the wires are wider and thicker, so resistance is lower.
- RCworst picks the variation that gives the highest resistance-capacitance product. In a typical corner definition the wires are narrower and thinner, so resistance is higher even though capacitance is a bit lower.
- Cbest and RCbest are the mirror images, giving the least capacitance and the smallest product. They make paths fast, which is what hold checks care about.
- Paths dominated by gate load and short wires are often worst in Cworst, because extra capacitance loads the driver. Paths with long, resistive wires are often worst in RCworst.
- Hold analysis uses fast corners, and crosstalk that speeds nets up is also checked there, so best corners matter as much as worst ones.
- Each RC corner is paired with PVT corners and modes into scenarios. That cross-product is what multi-corner multi-mode analysis manages, and it is why corners are chosen carefully rather than all run by default.
- Every corner needs its own extraction. Timing in one corner on another corner's parasitics is meaningless. Temperature is part of the picture as well. Metal resistance rises with temperature, so RC corners are usually defined at a temperature that matches the PVT corner they pair with, and a hot corner makes resistive paths worse still.
Common Mistake
The Trap: Signing off setup only in Cworst because "worst capacitance is the worst case". A long, resistive clock-to-data path passes in Cworst and fails in RCworst by 12 ps, where the higher resistance dominates. Both corners were needed for setup.
Follow-up Question & Model Response
"How would you decide which RC corners to include for a block?"
Candidate Model Response: Start from the foundry and methodology requirements, which usually name the corners needed for setup and hold. Then think about the design: blocks with long, resistive routes need RCworst, and short, load-dominated logic needs Cworst. Hold needs the best corners. Where the scenario count gets large, check which corners actually produce the worst slack for each path group and drop ones that never do, but only with evidence from full runs.
Practical Example
Tapeout Scenario: One path has a long M3 wire of 800 um, and another is short logic with a high fanout (illustrative). In Cworst, the long path has slack of +6 ps and the short path -3 ps. In RCworst, the long path drops to -8 ps because its wire resistance rose about 15%, while the short path improves to +2 ps. Neither corner alone finds both failures. For hold, RCbest shows a short scan path at -4 ps that no worst corner reveals. So the block needs Cworst and RCworst for setup and a best corner for hold, each with its own extracted parasitics. It helps to record, for each path group, which corner produced its worst slack. Over a few runs a pattern appears: long interconnect groups track RCworst, compact logic tracks Cworst, and hold tracks the best corners. That record is the evidence you need if the team later wants to trim the corner list to save runtime.
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