What are the four fundamental stages of the placement flow?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
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Short Answer
Production placement isn't one monolithic step — it runs as four distinct, purpose-built phases, and knowing which phase you're in tells you what kind of problem you're actually debugging. Global Placement comes first: an analytical engine treats the whole core as continuous space and spreads cells around to minimize estimated wirelength (typically half-perimeter wirelength) while avoiding density spikes. Cell coordinates here are still non-integer floats, and cells can still overlap — this stage is about rough positioning, not legality.
Technical Explanation
- Production placement isn't one monolithic step — it runs as four distinct, purpose-built phases, and knowing which phase you're in tells you what kind of problem you're actually debugging.
- Global Placement comes first: an analytical engine treats the whole core as continuous space and spreads cells around to minimize estimated wirelength (typically half-perimeter wirelength) while avoiding density spikes. Cell coordinates here are still non-integer floats, and cells can still overlap — this stage is about rough positioning, not legality.
- Specialized Physical Cell Insertion comes next: this is where non-logical manufacturing cells get inserted — well-tap cells (needed to prevent latchup) placed in a regular pitch array, and endcap cells placed at row and boundary terminations.
- Legalization then snaps every floating cell onto a real, valid row site: it fixes site orientation (flipping rows N/FS so shared VDD/VSS rails line up correctly), eliminates every instance overlap, and verifies pin-access clearance — this is the stage that turns "roughly placed" into "physically legal."
- Pre-CTS Optimization (
place_optin ICC2) is the final stage: it builds high-fanout net trees, sizes standard cells for timing, inserts buffers on critical paths, swaps multi-Vt thresholds for power, and re-stitches scan chains using the ScanDEF — all before the clock tree is even built. - Understanding this sequence matters practically: a "cells overlapping" complaint after global placement is expected (legalization hasn't run yet), but the same complaint after legalization is a real bug.
Common Mistake
The Trap: Believing that place_opt performs global placement from scratch. place_opt is an incremental optimization pass that operates on an already globally placed and legalized layout.
Follow-up Question & Model Response
"What happens if you run legalization before well-tap cell insertion?"
Candidate Model Response: Inserting well-taps afterward will displace legalized standard cells, causing new overlap violations that force a disruptive re-legalization pass.
Practical Example
Step-by-Step Flow Script:
# 1. Insert physical boundary and well-tap arrays
add_tap_cell_array -master_cell_name WELLTAP -distance 25 -stagger
add_end_cap -lib_cell ENDCAP -mode boundary
# 2. Coarse global placement
create_placement -floorplan -congestion
# 3. Legalize placed instances
legalize_placement
# 4. Pre-CTS timing & logic optimization
place_optPnR Flow Mentor Guide
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