AdvancedQuestion 27 of 63Source: Synopsys PrimeTime User Guide: Specifying Internally Generated Clocks

How do you constrain a clock divider generated by a flip-flop?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A flip-flop that toggles on every rising edge of an input clock divides that clock's frequency by two, and PrimeTime needs a create_generated_clock (SDC) statement at its Q output so the tool knows the new clock's period and phase instead of treating that pin as an ordinary data output. For a clock derived from the rising edge of its master, -divide_by is enough; for one derived from the falling edge, or with an uneven duty cycle, -edges gives the control -divide_by cannot.

A SYSCLK port feeding two divider flip-flops FF1 and FF2; FF1 clocked directly showing a correct -divide_by 2 generated clock DIV2A, and FF2 clocked through an inverter showing why -edges {2 4 6} is needed instead for the falling-edge-derived DIV2B, with both waveforms drawn beneath — Technical Reference DiagramHow do you constrain a clock divider generated by a flip-flop?

Technical Explanation

A divider output is a clock, not data, and PrimeTime has to be told so. Without a generated-clock statement, the tool treats the flip-flop's Q pin as a normal register output, and nothing downstream gets timed against the divided frequency at all.
-divide_by covers the simple, rising-edge-based case. create_generated_clock -name DIVIDE -source [get_ports SYSCLK] -divide_by 2 [get_pins FF1/Q] (SDC) tells PrimeTime the new clock's edges are derived from the rising edges of SYSCLK at the source pin.
-divide_by only works when the generated clock is based on rising edges of the master. If the divider flip-flop's Q instead toggles on the master's falling edge, -divide_by cannot express that relationship, and -edges (SDC) is required instead.
-edges names which numbered edges of the master waveform become the new clock's edges. create_generated_clock -name DIV2B -source [get_ports SYSCLK] -edges {2 4 6} [get_pins FF2/Q] (SDC) builds a divide-by-2 clock from the master's falling edges, something -divide_by has no option for.
-edges is also what you need for a non-50% duty cycle divided clock. Because -edges lists exact numbered transitions of the master waveform, it can produce an asymmetric high/low time; -divide_by always assumes a clean, even division.
Both forms still need a -source pin. PrimeTime has to trace a real electrical path from that source pin to the generated clock's own pin to compute the source latency correctly; if no such path exists, the clock fails to expand during update_timing (PT).

Common Mistake

Using -divide_by for a divider that is actually built off the master clock's falling edge, because the design "divides by 2" and that option sounds like the right fit.
-divide_by silently assumes the rising edge of the master; applied to a falling-edge divider it produces a generated clock with the wrong phase, not an error.
Cost: a divided clock whose edges are shifted by half a period from the real hardware, corrupting every setup and hold check downstream of it until someone diffs the waveform by hand.

Follow-up Question & Model Response

A divider flip-flop's own clock pin is driven by the falling edge of the master, but you can still describe its output with -divide_by 2 by picking a different -source pin. Why would you do that, and what changes?

Candidate Model Response: If an inverter or another gate sits between the master port and the divider flip-flop's clock pin, that intermediate pin sees the master's edges already flipped, so its rising edges line up with what was originally a falling edge at the port. Sourcing the generated clock from that internal pin instead of the port lets -divide_by treat it as an ordinary rising-edge division again. The tradeoff is that the source latency calculation now runs through whatever logic sits between the port and that internal pin, so the generated clock's source-side timing is only as accurate as that intermediate path.

Practical Example

A design has a 2ns-period SYSCLK port and two divider flops. DIV2A is built from FF1, clocked directly by SYSCLK's rising edge, so create_generated_clock -name DIV2A -source [get_ports SYSCLK] -divide_by 2 [get_pins FF1/Q] (SDC) is correct. DIV2B is built from FF2, but FF2's clock pin is driven by the same SYSCLK port through an inverter, so its toggling is anchored to the falling edge; the correct statement is create_generated_clock -name DIV2B -source [get_ports SYSCLK] -edges {2 4 6} [get_pins FF2/Q] (SDC), naming the master's second, fourth, and sixth edges instead of trying to force -divide_by onto a falling-edge source.