What is a generated clock?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
A generated clock is a clock signal that is derived from a master clock (or from another already-generated clock) by some on-chip logic, such as a divider, a clock gate, a multiplexer, or an inverter, rather than coming directly from an external clock source.
Example
create_clock -name clk -period 1000 [get_ports clk] create_generated_clock -name clk_div2 -source [get_ports clk]
Why It Matters
Because a generated clock is built out of ordinary logic instead of being an external pin, STA needs to be explicitly told about the relationship between it and its source clock; that's exactly what the create_generated_clock command does, letting the tool correctly figure out its period and relationship to the master clock.
Command
create_generated_clock -name clk_div2 -source [get_ports clk]Mentor Note — Common Mistake
Don't leave a divided or gated clock undeclared and assume the tool will figure out the relationship on its own. If a generated clock's source isn't properly found, check_timing worked-example output specifically calls this out as a 'generated_clocks' warning category.
Continue learning free
Get a practical low-power chapter
Receive the existing “Low Power and Multivoltage Fundamentals” PDF chapter and its download link by email.
Continue practising