AdvancedQuestion 28 of 63Source: Synopsys PrimeTime User Guide: Extracted Timing Model (ETM)

How do you cascade multiple generated clocks from the same master clock?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

When one generated clock feeds another - for example a divide-by-2 clock that is itself divided again to make a divide-by-4 clock - each stage's create_generated_clock (SDC) should name the immediately preceding generated clock as its -master_clock (SDC) and -source, not the original master, so PrimeTime can trace the chain edge by edge instead of guessing. Chaining the definitions this way keeps each stage's source-latency calculation limited to the logic between that stage and the one before it.

Technical Reference DiagramHow do you cascade multiple generated clocks from the same master clock?
A three-stage clock cascade diagram: MCLK at port MCLKIN feeding reg1 to produce MCLK_div2, which feeds reg2 to produce MCLK_div4, each create_generated_clock arrow labeled with its -master_clock pointing to the immediately preceding stage rather than back to MCLK

Technical Explanation

  • A generated clock can itself be a master clock for another generated clock. -master_clock (SDC) explicitly tells PrimeTime which clock's edges the new generated clock is derived from, when more than one clock reaches the same source pin and the tool cannot infer it on its own.
  • Cascading through each intermediate stage keeps the source-latency path short and correct. create_generated_clock -name MCLK_div2 -master_clock MCLK -add -divide_by 2 -source MCLKIN [get_pins reg1/Q] (SDC), followed by create_generated_clock -name MCLK_div4 -master_clock MCLK_div2 -add -divide_by 2 -source reg1/Q [get_pins reg2/Q] (SDC), tells the tool MCLK_div4 derives from MCLK_div2's edges at reg1/Q, not from the original MCLK directly.
  • Referring every stage back to the original master instead loses the intermediate topology. If MCLK_div4 were defined with -master_clock MCLK and -source MCLKIN again, PrimeTime would have to re-derive the divide-by-4 relationship across both flip-flop stages at once, exactly the kind of ambiguous, multi-hop source network the tool is prone to reject.
  • -add keeps each new generated clock as a distinct object at its own pin. Without it, defining a new generated clock at a pin that already carries one overwrites the earlier definition instead of adding a second clock alongside it.
  • Cascaded generated clocks make the source network traceable for hierarchical extraction too. An extracted timing model (ETM) built from this block only keeps the generated clocks visible at its ports if their source network chain can be followed stage by stage; a chain that skips straight back to the original master frequently cannot be.
  • Unexpanded generated clocks show up as update_timing warnings. A broken or ambiguous source network between a generated clock and its declared master typically surfaces as an error during update_timing (PT), not silently.

Common Mistake

  • Defining every cascaded generated clock with -master_clock pointing back at the original master clock instead of at the immediately preceding generated clock in the chain.
  • This forces PrimeTime to resolve the whole multi-stage divider in one step instead of one well-defined stage at a time, which is a common cause of "unexpanded generated clock" warnings on multi-stage dividers.
  • Cost: a generated clock that fails to expand during timing update, silently dropping every path clocked by it from setup and hold checking until the warning is tracked down.

Follow-up Question & Model Response

If a third stage MCLK_div8 is added after MCLK_div4 in the same chain, what should its -master_clock and -source be, and why does getting this wrong compound across the whole chain?

Candidate Model Response: MCLK_div8 should name MCLK_div4 as its -master_clock and reg2/Q - the pin where MCLK_div4 is created - as its -source, continuing the same one-stage-at-a-time pattern as the first two links. Skipping a link, for example sourcing MCLK_div8 from MCLKIN with -master_clock MCLK, would force the tool to resolve three divider stages of ambiguity at once instead of one, and any edge-alignment mistake at an earlier stage would be silently absorbed into the next rather than flagged where it actually occurred. Keeping the chain explicit means a broken stage produces an error at that exact stage instead of a mysterious failure two stages downstream.

Practical Example

A block's reference clock MCLK enters at port MCLKIN with a 4ns period. reg1 divides it by two, and reg2 divides reg1's output by two again, giving a final divide-by-4 clock at 16ns. The SDC defines create_generated_clock -name MCLK_div2 -master_clock MCLK -add -divide_by 2 -source MCLKIN [get_pins reg1/Q] (SDC) for the first stage, then create_generated_clock -name MCLK_div4 -master_clock MCLK_div2 -add -divide_by 2 -source reg1/Q [get_pins reg2/Q] (SDC) for the second. When this block is later extracted as an ETM and instantiated at the top level, both generated clocks remain visible at the block's interface as instance_name/MCLK_div2 and instance_name/MCLK_div4, because the cascading topology gave PrimeTime a clean, stage-by-stage path to follow.

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