BeginnerQuestion 47 of 95Source: Synopsys PrimeTime User Guide: Specifying Clocks

How do you model a clock with an uneven duty cycle using the waveform option?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

By default, create_clock -period (SDC) assumes a perfectly even 50% duty cycle clock. To model a clock that is high or low for a different fraction of its period, add the -waveform option and list the exact rise and fall edge times yourself.

A clock waveform trace showing a 10ns period with the rising edge at 0 and falling edge at 7, labelled as a 70 percent duty cycle — Technical Reference DiagramHow do you model a clock with an uneven duty cycle using the waveform option?

Technical Explanation

A period value alone is not enough information for an uneven clock.

What the period alone assumes: with just -period 10 (SDC) and no waveform, the tool places the rising edge at time 0 and the falling edge at time 5 — an even 50/50 split of a 10ns cycle.
What -waveform adds: the option takes a list of two times, {rise fall}, letting the designer place those two edges anywhere inside the period instead of at the midpoint.
A concrete uneven example: create_clock -period 10 -waveform {0 7} CLK (SDC) makes the clock high from 0 to 7ns and low from 7 to 10ns — a 70% duty cycle instead of 50%.
Why duty cycle matters for setup and hold: a launch-to-capture setup check and a same-edge hold check both depend on exactly when each edge lands, so a skewed duty cycle shifts both required times, not just one.
Where an uneven duty cycle actually comes from: it usually is not arbitrary — a PLL or clock divider circuit in the design genuinely produces a non-50% waveform, and the SDC constraint has to describe that real behavior, not an idealized one.

Common Mistake

The Trap: leaving a clock at the default 50% waveform because the real hardware clock is not actually even.

A designer copies a create_clock -period (SDC) line from another block without adding -waveform, assuming any 50/50 approximation is close enough.
The real PLL output is 65% high, 35% low — every setup and hold check for that domain is computed against the wrong edge times, and the error stays hidden until the constraint is finally corrected.

Follow-up Question & Model Response

Does an uneven duty cycle always make setup or hold worse? Candidate Model Response: It depends on which check and which direction the duty cycle shifts. Moving the falling edge later gives the high phase more time, which can help a path that launches on that edge but can also tighten the hold margin at the next active edge, since the two edges no longer sit at their default half-period spacing. There is no single rule — the designer has to check the actual edge times against the specific paths in that clock domain rather than assume uneven duty cycle is automatically safer or riskier.

Practical Example

A clock divider circuit outputs a 10ns period clock that is high for 7ns and low for 3ns. The SDC line reads create_clock -period 10 -waveform {0 7} -name CLK_DIV [get_ports CLK_DIV], so report_clock_timing (PT) shows the rising edge at 0, 10, 20... and the falling edge at 7, 17, 27..., matching the real circuit exactly.

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