BeginnerQuestion 52 of 95Source: Synopsys PrimeTime User Guide: Specifying Clocks

What is clock sense, and what does it mean for a clock to trigger on the falling edge?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Clock sense describes which edge direction of a clock signal a flip-flop actually reacts to — rising-edge-triggered or falling-edge-triggered. Most designs use rising-edge flops, but a design can deliberately use falling-edge flops, often to build a double-data-rate interface or to relax a tight setup path.

A clock waveform with one flip-flop capturing on the rising edge and a second flip-flop capturing on the falling edge, half a period later — Technical Reference DiagramWhat is clock sense, and what does it mean for a clock to trigger on the falling edge?

Technical Explanation

A flip-flop only samples its data input at one specific moment per clock cycle, and clock sense says which moment that is.

What "positive-edge-triggered" means: the flip-flop's internal latch captures the data input the instant the clock transitions from low to high — the default assumption in most cell libraries.
What "negative-edge-triggered" means: a different flip-flop cell captures on the high-to-low transition instead, using the exact same clock signal but reacting to its other edge.
The tool reads sense from the library cell, not a guess: the Liberty (LIB) model for each flip-flop cell states which edge its clock pin is sensitive to, and the tool builds setup and hold checks around that stated edge automatically.
set_sense (SDC) is for genuinely ambiguous logic, not a plain inverter: the tool already tracks an ordinary inverting buffer's polarity on its own. It is needed only where the clock passes through a gate like an XOR, whose sense depends on another signal; set_sense -type clock -positive/-negative (SDC) then states which sense applies.
Why mixing edges is sometimes deliberate: a path that is tight on the rising edge can be re-timed onto a falling-edge-triggered flop, effectively giving it half a clock period of extra time to work with, at the cost of adding a genuine half-cycle timing relationship the designer must track.

Common Mistake

The Trap: assuming every flip-flop in a netlist is rising-edge-triggered because that is the common default.

A designer reviews a schematic quickly and assumes a flop's clock pin behaves like every other one they have seen, without checking the actual library cell.
A falling-edge flop hiding in the netlist shifts that path's real launch or capture moment by half a clock period, which can silently turn what looked like a comfortable setup margin into a real violation once the correct edge is accounted for.

Follow-up Question & Model Response

Does the tool need any extra SDC just to support a design that mixes rising- and falling-edge flops? Candidate Model Response: Usually not, because the flip-flop cell's own Liberty (LIB) model already tells the tool which edge that specific cell reacts to, and the tool applies the correct edge automatically wherever that cell is used. set_sense (SDC) is only needed for a genuinely ambiguous gate, such as an XOR whose other input decides whether it inverts — a plain inverting buffer never needs it, since the tool already knows its fixed polarity.

Practical Example

A DDR-style interface uses a positive-edge flip-flop to capture the even data bits and a negative-edge flip-flop, driven by the exact same CLK_IO clock, to capture the odd bits half a cycle later — doubling the effective data rate off a single clock.

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