What is clock propagation, and what does set_propagated_clock actually change?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Explanation
Before layout, STA typically assumes an idealized clock (arriving everywhere at the same time, zero skew). set_propagated_clock switches the tool to compute the clock's actual insertion delay through the real, built clock tree once clock tree synthesis (CTS) has produced that physical network.
Timing-path Walkthrough
Pre-CTS, every flop's clock pin might be treated as arriving at t=0. After CTS builds an actual tree with buffers and routing, applying set_propagated_clock lets the tool compute the true arrival time at each flop's clock pin, which now carries real skew between launch and capture flops — directly changing both the S term in the setup inequality and the S term in the hold inequality.
Command
set_propagated_clockSwitch-by-switch
No sub-switches are given in the notes; the command itself is the toggle applied once the
real clock network exists so the tool computes actual insertion delay from the physical
network.Expected Report Behavior
Clock path sections of report_timing move from flat, idealized zero-latency entries to perstage insertion delay reflecting the real buffer/wire tree, and skew values become nonzero and path-specific.
Mentor Note — Common Mistake
Leaving the clock idealized (never applying set_propagated_clock) after CTS, so every flop still looks like it receives the clock at t=0.
How To Debug
Compare clock path entries in report_timing before and after applying set_propagated_clock; real per-flop insertion delay and non-zero skew confirm propagation is active.
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