AdvancedQuestion 29 of 63Source: Synopsys PrimeTime User Guide: Timing PLL-Based Designs

How do you define the generated clocks needed for a PLL with a feedback divider?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A phase-locked loop (PLL) needs its output clock declared as a generated clock with -pll_feedback and -pll_output (SDC) so PrimeTime can compute the phase correction the PLL applies between its reference and feedback pins. If a flip-flop sits on the feedback path - dividing the PLL's output frequency back down to match the reference - that flip-flop's output also needs its own generated-clock definition, because the PLL's phase correction only works once the tool can trace the entire loop, sequential elements included.

A PLL block UPLL with reference pin REFC, output pin CLKO, and feedback pin FDBK; CLKO also feeds a divider flip-flop FFdiv whose Q output loops back into FDBK, with two create_generated_clock labels shown - one on CLKO with -pll_feedback/-pll_output, one on FFdiv/Q with -divide_by 2 — Technical Reference DiagramHow do you define the generated clocks needed for a PLL with a feedback divider?

Technical Explanation

A PLL reduces clock skew by matching the phase of its feedback pin to its reference pin. To model that correctly, create_generated_clock (SDC) needs the reference, feedback, and output pin information built into the definition, not just a plain source-and-multiply relationship.
-pll_feedback and -pll_output (SDC) identify the two pins that make the phase-correction loop close. -pll_output names the clock output pin whose phase is being corrected; -pll_feedback names the pin that feeds that correction back into the PLL.
create_generated_clock -name CLK_pll -source [get_pins UPLL/REFC] -pll_output [get_pins UPLL/CLKO] -pll_feedback [get_pins UPLL/FDBK] -multiply_by 2 [get_pins UPLL/CLKO] (SDC) declares a PLL whose output runs at twice the reference frequency, with the phase correction wired through FDBK.
A sequential divider on the feedback path needs its own generated clock too. If a flip-flop like FFdiv sits between the PLL output and the feedback pin, dividing the frequency back down, its output pin needs a second create_generated_clock -source [get_pins UPLL/CLKO] -divide_by 2 [get_pins FFdiv/Q] (SDC) so PrimeTime can trace the loop through that register instead of treating it as a break in the path.
Both the PLL output clock and the reference clock at the PLL's reference pin should be propagated. set_propagated_clock (SDC) on both is what lets PrimeTime actually apply the computed phase correction, rather than assuming an ideal, zero-latency network.
Getting the feedback chain wrong shows up as an incorrect or missing phase correction, not necessarily an error. The PLL adjustment depends on the tool being able to trace reference-to-feedback all the way through the loop; a missing generated clock on a feedback divider silently breaks that trace.

Common Mistake

Declaring only the PLL's output clock with -pll_feedback/-pll_output and forgetting that a sequential divider sitting on the feedback path needs its own separate create_generated_clock statement.
Without it, PrimeTime cannot trace the feedback loop through the divider flip-flop, so the phase correction the PLL is supposed to apply either does not compute or computes against the wrong reference.
Cost: a PLL that looks correctly modeled in the SDC still reports clock skew as if it had no phase correction at all, hiding margin the real silicon actually has - or worse, hiding a skew problem the real PLL cannot actually correct.

Follow-up Question & Model Response

Why does the master pin of the feedback divider's generated clock need to satisfy two specific conditions - its fanout reaching the feedback pin, and it lying on the feedback path - rather than just naming any convenient upstream pin?

Candidate Model Response: PrimeTime needs an unambiguous, traceable route from the PLL's output pin, through the divider, to the feedback pin, because the whole point of the exercise is computing the loop's phase correction accurately. If the chosen master pin's fanout does not actually reach the feedback pin, the tool has no way to confirm that timing at that pin has any bearing on the loop it is trying to correct. And if the pin does not lie on the feedback path itself, using it as a source could describe a clock relationship that looks plausible in isolation but does not correspond to what the real phase-locked loop is doing, defeating the purpose of modeling PLL feedback in the first place.

Practical Example

A PLL UPLL takes a 5ns reference clock at pin REFC and produces a doubled-frequency output at CLKO; a flip-flop FFdiv on the feedback path divides CLKO back down by two before it reaches FDBK. The SDC declares create_generated_clock -name CLK_pll -source [get_pins UPLL/REFC] -pll_output [get_pins UPLL/CLKO] -pll_feedback [get_pins UPLL/FDBK] -multiply_by 2 [get_pins UPLL/CLKO] (SDC) for the PLL itself, then create_generated_clock -name pll_FDBK_clk -source [get_pins UPLL/CLKO] -divide_by 2 [get_pins FFdiv/Q] (SDC) for the divider. Only with both definitions in place, plus set_propagated_clock on the reference and output clocks, does PrimeTime's PLL adjustment correctly cancel the divider's contribution to skew between the two flip-flop stages the PLL was inserted to synchronize.

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