IntermediateQuestion 57 of 112Source: Synopsys PrimeTime User Guide: Specifying Sense for Clock Signals

How do you fix a clock signal's polarity through an inverting or non-unate cell in the clock network with set_sense?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

The tool normally traces a clock signal's polarity automatically as it passes through the clock network, following each cell's known logic function. When a cell's function is not resolvable that way — a black-boxed cell or a non-unate function like XOR — set_sense -type clock -positive or -negative explicitly tells the tool whether the output tracks or inverts the reference clock's polarity at that point.

Technical Reference DiagramHow do you fix a clock signal's polarity through an inverting or non-unate cell in the clock network with set_sense?
A clock network diagram showing the main clock and a test-select signal feeding an XOR gate XOR1, with a set_sense -type clock -positive annotation on its output pin and the resulting waveform matching the input clock.

Technical Explanation

A clock signal's polarity — whether the design should treat it as rising or falling at a given point — can flip as it passes through an inverting cell in the clock network, and the tool needs to be told when that happens.

  • The tool normally traces clock polarity automatically through the clock network, following each cell's known logic function as the clock signal propagates from its source.
  • Some clock-path cells have a function the tool cannot resolve on its own — a black-boxed cell, a cell modeled without full functional information, or a non-unate function like XOR whose output does not have one fixed sense relative to a single clock input.
  • set_sense -type clock -positive or -negative (SDC) tells the tool explicitly how to treat the clock at that point — positive meaning the output tracks the same polarity as the reference clock input, negative meaning it is inverted.
  • Without it, an unresolved non-unate clock point can stop the tool from propagating the clock past that pin at all, or force a conservative assumption that may not match the real circuit.
  • This is different from a generated clock's -invert option, which is used specifically with divide-based generated clocks — set_sense applies more generally to any point in the network where the tool's automatic polarity tracing needs an explicit override.
  • Why it matters: getting the sense wrong at one gate can silently flip which edge downstream flip-flops are analyzed against, which changes every setup and hold check fed by that branch without producing an obvious error.

Common Mistake

The Trap: assuming the tool always resolves clock polarity correctly on its own, and only reaching for set_sense after seeing an outright propagation error.

  • A non-unate cell like an XOR gate used for clock inversion or test-clock muxing can propagate with an incorrect or overly conservative assumed polarity without necessarily throwing a hard error.
  • The wrong sense at one clock-network gate silently changes which edge every downstream flip-flop is analyzed against, so the failure mode is subtly wrong timing results, not a clear failure message pointing at the cause.

Follow-up Question & Model Response

A clock signal passes through an XOR gate used to combine it with a test-mode select signal, and the tool cannot resolve the output's polarity on its own. How do you fix that?

Candidate Model Response: I would apply set_sense -type clock -positive [get_pins XOR1/Z] (SDC) if the XOR gate's output is meant to track the same polarity as the incoming clock in the relevant mode, or -negative if it is meant to invert it. Since an XOR gate's output polarity genuinely depends on its second input, I would confirm which case applies for each specific analysis scenario, since the test-select input being high versus low could change which sense is actually correct at that pin. I would then verify with a targeted report_timing (PT) that downstream flip-flops are being checked against the intended edge.

Practical Example

A clock network includes an XOR gate, XOR1, combining the main clock with a test-mode select signal that is held at a fixed value of 0 in the functional scenario. Because the tool cannot resolve XOR1's output polarity automatically, the team applies set_sense -type clock -positive [get_pins XOR1/Z] (SDC) for that scenario, confirming that with the select signal held at 0, XOR1 passes the clock through unchanged. report_clock_timing (PT) then shows downstream flip-flops correctly analyzed against the same rising edge as the main clock source, rather than an unresolved or inverted one.

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