IntermediateQuestion 47 of 112Source: Synopsys PrimeTime User Guide: Specifying Internally Generated Clocks

How do you constrain a clock gated by a combinational cell, using create_generated_clock -combinational?

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By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A gated clock — the master clock passed through an AND or OR gate for power savings — is not dividing or multiplying edges the way a flip-flop-based divider does, so it needs its own generated-clock option. The -combinational flag on create_generated_clock tells the tool to treat the output as a direct, gated copy of the master clock rather than trying to count edges.

Technical Reference DiagramHow do you constrain a clock gated by a combinational cell, using create_generated_clock -combinational?
A schematic of an AND gate ICG1 gating a 500MHz master clock with enable EN, labeled with the -combinational generated clock definition and a set_case_analysis value fixing the enable pin for the active scenario.

Technical Explanation

A generated clock is a second create_clock-like definition for a clock signal built inside the design, and -combinational tells the tool the generating logic is pass-through gating, not a clock-edge divider.

  • Most generated clocks come from sequential logic, like a flip-flop dividing a clock in half. The tool derives their edges by counting master-clock edges, using -divide_by or -edges (SDC).
  • A gated clock is different: it is the master clock passed through a combinational cell, usually an AND or OR gate used for clock gating to save power, with no edge-counting involved at all.
  • -combinational (SDC) tells the tool to treat the generated clock as a direct, gated copy of the master clock rather than trying to divide or multiply its edges.
  • The tool still needs a valid electrical path for the edges to propagate through the gate. If the enable signal blocks the gate at the moment an edge would pass, the tool needs that condition modeled separately, usually with set_case_analysis (SDC) on the enable pin during the relevant mode.
  • Getting this wrong looks like a broken clock, not a missing option. Defining a gated clock with -divide_by 1 instead of -combinational can still simulate as an edge-for-edge copy in some cases, but it misrepresents the actual gating structure and can miss glitches the gate could introduce.
  • Why it matters: clock gating is one of the most common low-power techniques, so getting the generated-clock definition right for every gated branch is a routine but easy-to-miss step in constraining a real design.

Common Mistake

The Trap: defining a gated clock with a divide or multiply factor of 1 instead of -combinational, because the edges happen to line up in a quick check.

  • A divide-by-1 definition can look identical to a combinational one when the enable is always on, but it misrepresents the actual gating cell in the design and does not correctly account for the gate's own propagation delay in the clock path.
  • If the gate ever glitches or the enable timing is not separately verified, a divide-by-1 definition gives no signal that anything unusual is happening at that gate — the -combinational option at least reflects the true structure being timed.

Follow-up Question & Model Response

Your design has an AND-gated clock enable that is only asserted during a specific power mode. How do you make sure timing analysis matches that mode correctly?

Candidate Model Response: I would define the gated clock with create_generated_clock -source [get_pins AND1/A] -combinational [get_pins AND1/Z] (SDC) so the tool knows the output is a direct gated copy of the master clock. Separately, I would use set_case_analysis 1 [get_pins AND1/B] (SDC) on the enable pin for the scenario where that power mode is active, so the tool has a valid electrical path for the clock edges to propagate through the gate during analysis. Without the case analysis, the tool may not find a consistent path for the generated clock's edges if the enable is left toggling in the same scenario.

Practical Example

A block has an AND gate, ICG1, gating the 500MHz core clock with an enable signal EN. The team defines create_generated_clock -source [get_pins ICG1/A] -combinational -name GATED_CLK [get_pins ICG1/Z] (SDC), then applies set_case_analysis 1 [get_pins ICG1/B] (SDC) for the active-mode scenario so the gate's output edges have a defined path during analysis. A separate low-power scenario applies set_case_analysis 0 on the same pin, correctly removing GATED_CLK from timing entirely while the block is clock-gated off.

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Related STA questions

BeginnerWhat is a generated clock?IntermediateHow do you define a generated clock correctly, and what goes wrong if you use create_clock instead on a divided clock?BeginnerWhat is set_case_analysis, and when would you tie a pin to a fixed value?IntermediateWhy must a generated clock's master clock be named explicitly with -master_clock when its source pin receives multiple clocks?