IntermediateQuestion 56 of 112Source: Synopsys PrimeTime User Guide: Defining Multiple Clocks on the Same Pin

How do you define two mode-dependent clocks on the same port using create_clock -add?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

By default, a second create_clock definition on a port that already has one replaces the first. The -add option keeps both instead, which models a port reached by more than one clock through an upstream mux — but only the clock active in a given mode should actually be used, so the mux selection also needs a case analysis or a mode-specific scenario to avoid two live clocks conflicting on one node.

Technical Reference DiagramHow do you define two mode-dependent clocks on the same port using create_clock -add?
A clock mux SEL1 feeding port CLK_PORT with two labeled create_clock definitions, FUNC_CLK and TEST_CLK, and two scenario boxes each showing a different case_analysis value fixing the mux to select one clock at a time.

Technical Explanation

A single physical port can legitimately need two different clock definitions if the design multiplexes which clock actually reaches it, one per operating mode.

  • By default, defining a second clock on a port that already has one overwrites the first. The tool assumes you are correcting or replacing the earlier definition unless told otherwise.
  • -add (SDC) on create_clock tells the tool to keep both definitions instead of replacing one. This models a port that is legitimately reached by more than one clock, typically because a mux upstream selects between sources depending on mode.
  • Both clocks exist in the timing database at the same time, but only the one active in a given scenario or mode should actually be used for analysis — the other needs to be disabled for that scenario, usually through a case analysis on the selecting mux or a separate mode-specific SDC file.
  • This differs from a generated clock relationship. A generated clock derives its properties from a master clock automatically; two -add-ed clocks on the same port are independent definitions with no derived relationship between them at all.
  • Reports on a port with two added clocks show both, unless filtered. report_clock (PT) or get_clocks (PT) filtered by name is the way to confirm exactly which clocks the tool associates with that port.
  • Why it matters: using -add without also handling which clock is actually valid in each mode gives the tool two live clocks on one physical node, which can create nonsensical paths between them if left unresolved.

Common Mistake

The Trap: using create_clock -add to define both mode clocks on a shared port, but forgetting to resolve which one is actually selected in each analysis scenario.

  • Leaving both clocks fully active at once gives the tool two independent clocks on the same physical node, which can generate meaningless inter-clock paths that were never physically possible.
  • The fix is not just -add — the mux selecting between the two clock sources also needs its own case analysis or mode-specific scenario so only one clock is live in any given run.

Follow-up Question & Model Response

A test port receives either the functional system clock or a separate ATE test clock, selected by a mux, depending on mode. How do you set this up?

Candidate Model Response: I would define both clocks on the port using create_clock -name FUNC_CLK -period 2 [get_ports CLK_PORT] and create_clock -name TEST_CLK -period 20 -add [get_ports CLK_PORT] (SDC), so both are available in the timing database. Then, for the functional-mode scenario, I would apply a case analysis fixing the mux select pin to choose FUNC_CLK's path, and for the test-mode scenario, fix it the other way for TEST_CLK. This keeps each scenario's analysis using exactly one live clock on that port, avoiding any inter-clock paths between FUNC_CLK and TEST_CLK that could never actually occur in silicon.

Practical Example

A shared port CLK_PORT receives either a 500MHz functional clock (2ns period) or a 50MHz ATE test clock (20ns period), selected by mux SEL1. The team defines create_clock -name FUNC_CLK -period 2 [get_ports CLK_PORT] (SDC) as the base definition, then create_clock -name TEST_CLK -period 20 -add [get_ports CLK_PORT] (SDC) to keep both. The functional scenario applies set_case_analysis 0 [get_pins SEL1/S] (SDC) to select the functional path, while the test scenario applies set_case_analysis 1 on the same pin, so report_clock (PT) confirms only one of the two clocks is actually active in each scenario's analysis.

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