What is the difference between an ideal clock and a propagated clock?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
An ideal clock is modeled as reaching every flop instantly, or with just a fixed, uniform latency number, before any real clock tree/network has even been built. A propagated clock is timed through the actual, built clock network, capturing real insertion delay and real skew between different flops.
Example
Early in the design flow (RTL, synthesis, placement stages), STA runs with an ideal clock and estimated wires. Later, once clock tree synthesis (CTS) has built the real clock distribution network, STA can use propagated, real clocks.
Why It Matters
Ideal clocks are a convenient simplification for early-stage analysis when the physical clock network doesn't exist yet. But real clock trees have wire delay and branching, so different flops receive the clock signal at slightly different times (skew) and after some delay (insertion delay). Propagated clock analysis is what reflects the truth the chip will actually see.
Mentor Note — Common Mistake
Don't rely on ideal-clock results as your final signoff answer. Once the clock tree exists, you need propagated clock timing to see real skew and insertion delay effects, which ideal modeling completely hides.
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