BeginnerQuestion 43 of 95Source: Synopsys PrimeTime User Guide: Design Rule Checking

What is the difference between a setup/hold check and a design rule check like max transition?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A setup or hold check compares two clock-relative times on a path and produces slack — a value that can be positive or negative. A design rule check (DRC) like max transition compares a single measured value against a fixed library or user limit, with no clock relationship involved at all.

Side-by-side comparison table of a setup/hold slack check against a max-transition design rule check, showing what each one measures — Technical Reference DiagramWhat is the difference between a setup/hold check and a design rule check like max transition?

Technical Explanation

Both kinds of check can fail a design, but they are answering different questions.

What a setup/hold check measures: the arrival time of data relative to when the clock captures it. It always produces a slack number that depends on two clock edges.
What a design rule check measures: a physical property of one signal on its own — how slow its edge is (transition, or slew) or how much capacitance it is driving — compared against a fixed limit the library or the designer sets.
No clock is involved in a DRC: set_max_transition (SDC) sets a transition limit that applies whether the signal is a clock, a data net, or a reset — the clock's period never enters the comparison.
Why max transition exists at all: a very slow-edged signal makes a cell's delay number less accurate and can even make the cell behave unpredictably, so the limit exists to keep every signal inside the range the library was characterized for.
Both show up as violations in signoff: a design can pass every setup and hold check and still fail signoff because of a DRC violation on an over-loaded net, so a clean setup/hold report alone does not mean the design is done.

Common Mistake

The Trap: checking only slack numbers and assuming a clean timing report means the design is finished.

A designer runs report_timing (PT), sees no negative slack anywhere, and declares timing closed without ever running a DRC check like report_constraint (PT).
A net can be quietly violating max transition or max capacitance the whole time, which later shows up as a real silicon reliability or noise problem that setup/hold never caught.

Follow-up Question & Model Response

Can a max transition violation cause a setup or hold failure by itself? Candidate Model Response: Yes, indirectly. A slow transition on a signal that feeds a gate's input makes that gate's own output delay less predictable, and library timing tables can even become inaccurate outside their characterized range. So a DRC violation upstream can inflate a downstream cell's delay enough to turn a previously passing setup path into a failing one, even though the two checks are measuring different things.

Practical Example

A clock buffer drives a net with 40 fanout loads and its output transition measures 0.9ns, above the library's 0.6ns max-transition limit. The setup report on every downstream path still shows positive slack, but the design fails signoff on that one DRC violation until the net is re-buffered.

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