BeginnerQuestion 42 of 95Source: Synopsys PrimeTime User Guide: Timing Arcs and Delay Calculation

What is a timing arc, and why do rising and falling edges have different delays?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A timing arc is the delay from one specific input transition on a cell to one specific output transition — for example, input rising to output falling. A single gate has several arcs, and the tool tracks each one separately because the delay is not the same for every combination.

Technical Reference DiagramWhat is a timing arc, and why do rising and falling edges have different delays?
An inverter chain of four stages with each arc labelled by direction and its own rise or fall delay number

Technical Explanation

A cell like an inverter or a NAND gate does not have just one number for its delay.

  • Why one gate has several arcs: an inverter has two arcs — input rise to output fall, and input fall to output rise — because the transistors doing the pulling-up and pulling-down are physically different devices.
  • Rise and fall are rarely symmetric: an NMOS transistor pulling a node low usually drives more current than the PMOS transistor pulling it high, of the same drawn width, so one edge direction is naturally faster.
  • The library stores both directions: the standard cell timing library (Liberty) keeps a separate delay table for each arc, indexed by input transition and output load.
  • Multi-input cells have one arc per input pin: a two-input NAND gate has four arcs in total — each input, each output direction — and the slowest one for a given switching input is what the tool uses for that path.
  • Why it matters for the path delay: a timing path is a chain of arcs end to end, so the tool must know which edge direction is active at each stage to add up the right numbers, not just a single average delay per cell.

Common Mistake

The Trap: assuming a gate has one delay number and using the rise delay everywhere.

  • Someone estimates a path's total delay by multiplying a gate's rise-delay number by the number of stages, ignoring that half the stages actually switch in the fall direction.
  • This either overestimates or underestimates real delay, because a chain of inverters alternates rise and fall at every stage, and the two directions are not equal.

Follow-up Question & Model Response

Does the tool always pick the worse of rise and fall delay to be safe? Candidate Model Response: No — the tool tracks which direction is actually happening at each stage of a specific path, because an inverting gate flips the direction at every stage. It only takes the worse of the two when the signal's polarity truly is ambiguous, for example at a path startpoint with no known prior state. Picking the worse arc everywhere would make every report overly pessimistic and would not match silicon.

Practical Example

An inverter chain of four stages has each stage's rise delay at 45ps and fall delay at 60ps. A rising input at stage 1 produces a falling output (60ps), which becomes a rising input at stage 2 (45ps), and so on — total delay is 45+60+45+60=210ps, not four times either number alone.

Complete STA Handbook

Get the complete 10-chapter STA handbook covering setup/hold margins, clock modeling, OCV/POCV, crosstalk noise, and PrimeTime closure.

Explore Complete STA Guide →
VLSI Physical Design Planning Handbook — fourteen chaptersDesign PlanningFourteen chapters, floorplanning through timing budgets. →

Continue practising

Related STA questions

BeginnerWhat is cell delay?BeginnerWhat is slew (transition time), and why does it matter?BeginnerWhat is a standard cell timing library (Liberty), and what does it contain?BeginnerWhat is NLDM (Non-Linear Delay Model)?