BeginnerQuestion 63 of 95Source: Synopsys PrimeTime User Guide: Operating Conditions and Derating

What is derating, and why does PrimeTime multiply delays by a margin?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Derating is the practice of scaling a calculated delay up or down by a fixed factor to account for the fact that two identical-looking gates on the same chip do not switch at exactly the same speed. PrimeTime applies a derate factor with set_timing_derate (SDC) so setup and hold checks assume a small, safe amount of extra variation instead of trusting one single delay number for every instance. It is the tool's way of modeling on-chip variation without having to know the exact speed of every gate up front.

Setup check timing diagram showing late derate applied to the launch/data path and early derate applied to the capture clock edge, with a 1.05x and 0.95x factor labeled — Technical Reference DiagramWhat is derating, and why does PrimeTime multiply delays by a margin?

Technical Explanation

Manufacturing is never perfectly uniform, so this is what derating does about it.

Two "identical" instances of the same standard cell, placed a few hundred microns apart on the same die, can end up with slightly different threshold voltage, so the same input produces slightly different delay.
Derating multiplies the reported delay by a factor above 1.0 for the slow, late direction and below 1.0 for the fast, early direction, using set_timing_derate -late 1.05 and set_timing_derate -early 0.95 (SDC).
The tool applies late derate wherever arriving late is the risk (the launch and data path in a setup check) and early derate wherever arriving early is the risk (the capture clock path in that same check).
Turning on set_timing_derate implicitly switches the design into on-chip variation mode, the same mode set_operating_conditions -analysis_type on_chip_variation (PT) selects directly.
Without derating, the same "typical" delay number gets reused everywhere, quietly assuming every instance of a cell runs exactly as fast as every other instance.

Common Mistake

The Trap: assuming one flat derate value should cover cell delay and net delay the same way.

PrimeTime lets a cell-delay derate and a net-delay derate be set independently with -cell_delay and -net_delay (SDC); leaving both the same hides that wire delay and gate delay vary for different physical reasons.
Skipping this split usually means margin is too tight on the component that varies more and wasted on the one that varies less.

Follow-up Question & Model Response

If derating always makes setup analysis more conservative, why not derate everything by one large fixed percentage and skip on-chip variation setup?

Candidate Model Response: A single large flat derate protects against far more variation than actually exists between two nearby cells, applying the same worst-case percentage to every path regardless of stage count or distance. That wastes margin where launch and capture clock paths share most of the same route, and an aggressive clock period cannot afford to give up margin it does not need. This is the motivation for AOCV and POCV, which scale the derate down for paths sharing more clock structure.

Practical Example

On a 60-stage clock tree where two flops share the first 40 buffer stages, a flat derate of 1.10 applied everywhere adds 10% margin even though the shared stages should track almost exactly. Applying set_timing_derate -late -cell_delay 1.10 with a smaller -net_delay derate of 1.04 recovers part of that margin, since wires vary less than threshold voltage, freeing about 15ps of setup slack.

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