How do you use a virtual clock to constrain a chip I/O interface that has no on-chip clock source?

Short Answer

A virtual clock is a create_clock definition with no real source pin — it never propagates anywhere in the design, but it still gives set_input_delay and set_output_delay a -clock reference to compute setup and hold windows against. This is the standard way to constrain an interface to an external chip whose own clock never physically reaches your design.

Technical Explanation

A virtual clock is a create_clock definition with no real source pin in the design — it exists only to give the tool a timing reference for signals crossing the chip boundary.

• The tool needs a clock reference for every input and output delay it checks. set_input_delay and set_output_delay (SDC) both require a -clock argument, so if no on-chip clock actually captures or launches that boundary signal, a virtual clock fills that role instead.
• A virtual clock is created the same way as a real one, just without a source pin attached. create_clock -name vclk -period 5 [list] (SDC) with an empty or non-existent source list produces a clock object the tool can reference, but that never propagates anywhere in the netlist.
• This is the normal case for interfaces to external chips with their own clocking. A memory controller's data bus, timed relative to a DDR memory's own internal clock, has no matching on-chip clock pin — the virtual clock stands in for that external timing relationship.
• The virtual clock's period and edges still have to be accurate, since the tool computes real setup and hold windows from them, even though the clock itself never toggles any real gate in the design.
• A virtual clock never appears as a source in report_clock and cannot drive a real generated clock, since there is no propagation path for the tool to trace — it exists purely as a timing reference object.
• Why it matters: without a virtual clock, a boundary signal with no local clock reference would need set_input_delay/set_output_delay pointed at some real on-chip clock that has no actual relationship to the external timing, producing a misleading or impossible-to-interpret check.

Follow-up Question & Model Response

A DDR memory interface has a data signal timed relative to the memory device's own internal clock, which never enters your chip as a net. How would you constrain that input?

Candidate Model Response: I would define a virtual clock matching the memory's clock period and edges with create_clock -name mem_vclk -period 5 -waveform {0 2.5} (SDC), giving it no source pins so it stays purely a reference object. Then I would apply set_input_delay -clock mem_vclk 1.2 [get_ports DATA*] (SDC) using the delay value from the memory's datasheet relative to its own clock edge. This keeps the check tied to the real external timing relationship instead of borrowing an unrelated on-chip clock that would pull in clock-tree effects that have nothing to do with the memory interface.