What is the stack effect (transistor stacking), and how does it reduce subthreshold leakage in an idle logic gate?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Definition
The stack effect is the reduction in subthreshold leakage current that occurs naturally when two or more transistors are connected in series (stacked) and more than one of them is off, because the internal node between the stacked transistors settles to a small positive voltage that reverse-biases the lower transistor's source-body junction and raises its effective threshold voltage.
Mentor Explanation
Consider a 2-input NAND gate's pull-down network: two NMOS transistors in series to ground. When both inputs are low (both transistors off), a tiny subthreshold leakage current still flows, and that current has to flow through both series transistors — but because the internal node between them can only be supplied by the (very small) subthreshold currents themselves, it settles to a small positive voltage rather than staying at 0V. That small positive voltage at the internal node reverse-biases the lower transistor's source-to-body junction (raising its Vt via the body effect) and also reduces its Vgs, both of which push its subthreshold current down further — a self-limiting effect. The result is that a stack of N series off-transistors leaks significantly less than N times a single off-transistor's leakage; the reduction is often an order of magnitude or more for two or three stacked devices, compared to a single equivalent-width transistor.
Example
A designer choosing between a wide 4-input NAND (deep stack) implemented directly versus decomposing it into two cascaded 2-input NANDs can find that, purely from a leakage standpoint, keeping the deeper stack intact (when all 4 inputs are commonly low together during idle) leaks less than the decomposed version, because the decomposed version breaks up the beneficial series-stacking.
Why It Matters
This is one of the few leakage-reduction techniques that requires no extra circuitry, no extra control signals, and no extra area beyond what a normal multi-input gate already has — it's a free byproduct of series transistor topology. Some low-power synthesis flows deliberately favor logic restructuring that increases natural transistor stacking on inactive paths (input vector control / self-stacking), specifically to exploit this effect without paying the cost of an explicit sleep transistor.
Command
# Conceptual illustration, not an EDA command:
# single off transistor: I_leak ~= I0
# two stacked off transistors: I_leak ~= I0 / 10 (order-of-magnitude reduction, process-dependent)
# exploited via "input vector control": choose the idle input pattern that maximizes stackingCommon Beginner Mistake
Assuming leakage scales purely with the total number of off transistors regardless of topology (i.e., that two stacked off transistors leak "twice as much" as one). In fact stacked off transistors leak less per-transistor than an isolated off transistor of the same width, due to the self-reverse-biasing internal node — ignoring this can lead to overestimating leakage in a hand analysis, or missing a legitimate low-cost leakage-reduction opportunity during logic restructuring.
Low-Power & UPF Handbook
Master Low-Power VLSI & Multivoltage Design
Read the complete low-power guide library covering power domains, level shifters, isolation clamps, state retention, and UPF signoff verification.
Continue practising