DRC- and LVS-clean chips can still fail in silicon. What does signoff miss?

Short Answer

DRC checks shapes against geometric rules and LVS checks connectivity against the netlist. Neither checks how the chip behaves electrically over time or under real activity. Dynamic IR under real vectors, EM lifetime, ESD discharge paths, litho hotspots that pass rule checks, density gradients and thermal hotspots all sit outside those two runs, so each needs its own analysis and its own owner.

Technical Explanation

• Dynamic IR under real activity. Vectorless analysis in RedHawk builds a switching scenario from toggle rates and constrains it to the average chip power given in the GSR, which is realistic on average but can miss a short burst where many flops switch together. A burst droop slows paths that passed STA and shows up as failures only at speed.
• EM lifetime. EM checks compare average, RMS and peak current density with foundry limits, and Black's equation ties mean time to failure to current density and temperature. A grid that passes at the nominal temperature can fail years later in a hot corner of the die.
• ESD discharge paths. An ESD strike drives a large current through the pad, clamp and supply network. DRC can check that a clamp exists, but only a resistance check such as perform esdcheck (RH) shows whether the bump-to-clamp-to-bump loop is low enough to protect the gates.
• Litho hotspots. Rule-based DRC checks each rule on its own. Some pattern combinations are legal by every rule but print poorly, which is why foundries add DFM and pattern checks and recommend fixing them when area allows.
• Density gradients. A density rule checks each window against a minimum and maximum. A dense window beside a nearly empty one can pass both limits and still polish unevenly in CMP, thinning metal on one side.
• Thermal hotspots. Temperature raises wire resistance, raises leakage and lowers the allowed EM current, so thermal analysis with analyze_thermal (ICC2) links back to IR and EM.
• Timing under supply noise. STA uses the library voltage, while real cells see that voltage minus the local drop. A block that meets timing at nominal supply can fail when its local drop exceeds the margin set aside for it.
• Power-gating wake-up. When a switched domain turns on, its capacitance charges from the always-on supply. That rush current can pull down neighbouring always-on logic, and only a ramp-up analysis such as perform analysis -lowpower (RH) shows how far. Static and dynamic runs of the fully-on state never exercise it.

Follow-up Question & Model Response

"Which of these gaps would you close first on a new high-performance block, and why?"

Candidate Model Response: Dynamic IR under a realistic worst-case window, because it directly erodes timing margin and is the most common cause of at-speed failures that STA did not predict. I would run vectorless first to find weak areas, then a VCD run on the highest-power window from functional simulation. EM comes next, run on the same currents and at the operating temperature from thermal analysis. ESD is usually owned by the IO team, but I would confirm that their resistance checks ran on the final GDS, not an earlier version.