BeginnerQuestion 183 of 187Source: Synopsys ICC2 Implementation User Guide X-2025.06-SP2: Chip Finishing and Design for Manufacturing (Inserting Redundant Vias); Synopsys IC Validator User Guide S-2021.06-SP2: Pattern Matching

What are DFM checks, and why are they "recommended" rather than mandatory?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

Short Answer

DFM checks are foundry rules that go past the DRC minimums: larger via enclosures, redundant vias, longer line ends, wider spacing where there is room, and pattern matching for shapes known to lower yield. A layout that misses a recommended rule can still be built, so the foundry does not make these pass or fail; each fix buys yield at a cost in area, tracks or timing. You apply them where they are cheap and skip or waive them where they would hurt the design.

Technical Reference DiagramWhat are DFM checks, and why are they "recommended" rather than mandatory?
Two versions of the same wire and via: one at minimum DRC values with a single via and minimum enclosure, and one with a double via, extended enclosure and longer line end, with a small ledger comparing via count, track use and relative yield risk.

Technical Explanation

  • DRC rules are the minimums the foundry needs to accept the layout. DFM rules raise the chance that each feature prints and connects as drawn. Yield is statistical, so a single minimum-size via usually works, but millions of them add up to measurable loss.
  • Redundant vias are the best-known DFM fix. The ICC2 guide calls redundant via insertion an important DFM feature: Zroute optimizes via count as well as wire length at each routing stage, and the result is measured by the redundant via conversion rate. Fewer unoptimized single vias is usually better for DFM.
  • The cost is routability. The guide warns that choosing redundant vias only on DFM grounds can hurt routability, because a double via takes more space and can block neighbouring tracks.
  • Zroute supports DFM and design-for-yield optimization through a soft rule approach: soft rules are honoured when the cost is acceptable and relaxed when they would create real violations. That is the recommended-rule idea built into the router.
  • Pattern matching finds known yield detractors. IC Validator can use a foundry-certified DFM package, a pattern library with a matching runset, to search for hotspots and drive automatic repair and revalidation.
  • Categories vary by node and foundry. Metal density and some via rules are mandatory at advanced nodes even though they are about manufacturability, while enclosure extensions and extra vias stay recommended. The deck and the foundry's documentation decide which bucket a rule is in.
  • Customers sometimes turn recommendations into requirements, such as a minimum redundant via rate on clock nets, where a single failed via stops the whole chip.
  • Track DFM as numbers, not impressions: the redundant via conversion rate, the count of unoptimized single vias, and the count of pattern-match hotspots before and after repair. Those numbers let you compare blocks and show a reviewer where recommended rules were applied and where they were skipped.

Common Mistake

The Trap: Forcing near-100% redundant vias on the whole block after timing closure. The extra via shapes spread into congested regions, create new shorts and spacing violations, and shift wire RC on critical paths. The team spends a week closing DRC and timing again for a small yield gain that selective insertion on clocks and open areas would have captured with none of the rework.

Follow-up Question & Model Response

"How do you decide which recommended rules to apply?"

Candidate Model Response: Start with the foundry's own ranking: some DFM rules have a clear yield impact at the node and others are marginal. Apply the high-value ones where they cost little, such as redundant vias on clock and critical nets and in regions with free tracks. Skip them where they would add DRC or timing risk, and record the choice so reviewers can see it was deliberate. Recheck DRC and timing after any DFM pass, because every added shape changes the layout.

Practical Example

Tapeout Scenario: (illustrative) A block has 2.0 M vias with a 78% redundant via conversion rate. A post-route insertion pass raises it to 93%, leaving 140 k single vias. The pass also creates 3 shorts in a congested channel, so that region is excluded and the pass rerun: the rate settles at 92%, DRC is clean, and the clock nets reach 99% because they were given nondefault rules with double vias from the start. Timing is rerun on the new extraction and moves by less than 2 ps, so the pass is kept, and the excluded channel is written up as a deliberate skip.

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