What do ESD and latch-up checks protect against at signoff?

Short Answer

ESD checks confirm that every pad has a low-resistance discharge path through protection clamps, so a static discharge during handling, test or assembly flows through the clamps instead of through thin gate oxide. Latch-up checks confirm that well and substrate taps and guard rings are close enough that the parasitic PNPN structure inside CMOS cannot switch on and short VDD to VSS. Both protect against failures that timing, LVS and ordinary spacing checks do not see, and both are signed off with foundry rules and resistance-based checks.

Technical Explanation

• ESD events are described by three models in the RedHawk manual: Human Body Model, Machine Model and Charged Device Model. The damage they cause includes oxide punch-through, junction burnout and metallization burnout.
• Full transient ESD simulation of a whole chip is not practical, so static checks measure the resistance of each discharge path assuming the clamps are on: bump to bump, clamp to clamp, and core instance to clamp. A path far above the threshold resistance means there is no good route for the discharge.
• In standalone RedHawk this is PathFinder, run with perform esdcheck -rule <rules_file> -clamp <clamp_file> (RH). Clamp I-V curves must be defined, and the checks cover clamp placement relative to pads and cells as well as current density on the discharge paths. Standalone RedHawk needs an Ansys licence.
• CDM is the case that reaches into the core: the chip itself holds the charge and discharges through a grounded pin, so large custom macros need a low-resistance path to a clamp through the power grid.
• Latch-up comes from the parasitic PNP and NPN transistors formed by wells and substrate. If current injection raises the well or substrate voltage enough, the pair turns on and holds VDD shorted to VSS until power is removed.
• Well taps keep those well and substrate resistances low. Placement handles tap spacing with tap cells; signoff checks the rules in the foundry deck, such as maximum distance from diffusion to a tap and guard rings near I/O. Rule values are foundry-confidential.
• ESD structures usually come from the I/O library, but the block engineer still owns what can break them: PG width to clamps, clamps staying connected after ECOs, and tap cells surviving filler and ECO changes.
• Both checks read the final layout, so they belong after the last ECO. An ESD path that was fine at floorplan can lose a strap to a late routing change, and a latch-up rule can break when a filler swap removes a tap, so passing them once early proves little.

Follow-up Question & Model Response

"Why is CDM harder to protect against at block level than HBM?"

Candidate Model Response: In HBM the charge enters at a pad and leaves through another, so the path is mostly pad, clamp and I/O ring. In CDM the chip body holds the charge and discharges through one grounded pin, so current flows from inside the core, through the power grid, toward that pin. The RedHawk manual notes that a large custom macro may have no obvious discharge path in the CDM case. That makes block PG resistance to the nearest clamp part of ESD signoff, not only an I/O concern.