What is an isolated via, and why is it a yield risk?

Short Answer

An isolated via is a via with no neighbouring via close enough to meet the technology's requirement. Lithography and etch are tuned for vias that sit in a pattern, so a lone cut prints with more size variation and is more likely to come out resistive or open, and one open via on a signal net is a dead net. In ICC2 you set the search range per via layer and run signoff_fix_isolated_via -check_only true (ICC2) before you let the tool change anything.

Technical Explanation

• The check is about neighbours, not connectivity. A via can pass LVS and still be flagged, because the rule only asks whether another via exists within a distance on the same via layer.
• The foundry sets that distance per via layer and the value is node-specific and confidential. You give it to ICC2 through signoff.fix_isolated_via.isolated_via_max_range (ICC2), which is required and has no default. The syntax is { {via_layer1 distance1} ... } with mask names such as via1 and distances in microns.
• The command runs IC Validator through ICC2, so the IC Validator environment must be set up first and an IC Validator licence is needed.
• With -check_only true the command writes a summary report of isolated vias on each via layer and changes nothing. Without it, the default is to check and fix.
• Fixing works in steps: insert track-based dummy fill around each isolated via (existing fill is ignored unless you use signoff_fix_isolated_via -update_track_fill true (ICC2) with the earlier run's parameter file in -track_fill_runset_include_file (ICC2)), add fixing vias, then remove the fill shapes it did not use.
• Fixing vias are tried in a fixed priority order: first a via between an existing non-wide net shape and a fill shape, then extending the line end of a non-wide net shape and placing a via between the extension and a fill shape, and last a via between a wide metal shape and a fill shape. Routing rules, including double patterning, are honoured.
• The avoid_net_types option of signoff isolated-via fixing defaults to {clock pg}, so clock and PG nets are left alone. The block is not saved unless you add -save_design true or run save_block (ICC2). In very congested or very sparse blocks some vias may stay unfixed; they land in signoff_fix_isolated_via.err (ICC2).

What To Check

• Per-layer counts in the check-only summary report, before and after the fix run.
• That the range values match the current foundry deck revision for every via layer in the stack.
• Where the leftover vias in signoff_fix_isolated_via.err (ICC2) sit: congested channels, sparse areas, or clock and PG nets.
• A clean signoff_check_drc (ICC2) rerun over the fixed regions.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): Check-only after fixing reports 0 on every via layer, for example via1 180 to 0 and via2 95 to 0, and the DRC rerun is clean.
• Suspicious (illustrative): A small residue clustered in one place, such as 11 vias on via3 in a macro channel, or a layer showing zero because its range was never set.
• Hard stop: New DRC violations created by fixing vias, or a run made with ranges from an older deck revision that the foundry's check then contradicts.

What The Interviewer Is Testing

• Whether you know isolation is a density rule on via neighbours, independent of connectivity.
• Knowing the range option is required, per via layer, and that a check-only mode exists.
• Awareness of the fixing priority and that clock and PG nets are avoided by default.

Follow-up Question & Model Response

"Why does the tool avoid clock and PG nets by default when it fixes isolated vias?"

Candidate Model Response: The avoid_net_types option of isolated-via fixing defaults to {clock pg}. Clock nets are balanced for skew, and a line-end extension or extra via changes their RC after the tree has been signed off. PG nets are built by grid rules and feed IR and EM analysis, so editing them quietly would change results you already reviewed. For an isolated via on a clock net, change the list on purpose and recheck clock timing, or fix it by hand.