Why insert fill only when timing is nearly clean?

Short Answer

Metal fill adds floating metal next to, above and below signal wires, and every piece adds capacitance. That changes the parasitics and so the delays, usually slowing paths. If you fill while timing is still moving, each timing fix disturbs the fill and each fill pass disturbs timing, so the ICC2 guide says the block should be close to meeting timing, with few or no DRC violations, before fill goes in.

Technical Explanation

• Fill shapes are floating conductors. A signal wire with fill beside it on the same layer sees extra sidewall capacitance, and fill on the layers above and below adds area capacitance. The extra C slows the driver and the wire, so setup slack drops on those nets.
• Crosstalk coupling can change as well. Fill between two signal wires takes some of their direct coupling, but the total capacitance each wire sees still rises. The net effect depends on geometry, so it has to be extracted, not guessed.
• Before fill, extraction uses emulated fill: the TLUPlus model accounts for fill statistically. After fill, you can extract real fill: associate non-emulation TLUPlus files with the corners, then enable it with set_extraction_options -real_metalfill_extraction floating (ICC2). Mixing the two double-counts or misses fill.
• Each timing ECO after fill moves cells and wires, which means fill in those areas must be removed and reinserted. The guide gives incremental fill for modified regions, but many small ECO loops each need their own fill update and re-extraction.
• Timing-driven fill reduces the impact. With -nets (ICC2) or -timing_preserve_setup_slack_threshold (ICC2), signoff_create_metal_fill (ICC2) keeps fill away from critical nets; by default spacing to those nets is twice the minimum spacing from the technology file. It cannot be combined with TCD fill.
• A threshold that is too large makes too many nets critical, which leaves large empty areas and can cause density errors. signoff.create_metal_fill.fix_density_errors (ICC2) can repair those during timing-driven fill; it defaults to false.
• Hold can move too. Extra capacitance normally helps hold on the slowed paths, but it also changes clock-net delay when fill lands beside clock wires, which shifts skew. The guide provides signoff.create_metal_fill.fill_shielded_clock (ICC2) to control whether shielded clock nets are filled during timing-driven fill.
• The practical order is: close timing on emulated fill, insert fill, extract with real fill, run final timing, and make only small ECOs with incremental fill afterwards.

Follow-up Question & Model Response

"How would you protect critical paths from fill without leaving density violations?"

Candidate Model Response: I would use timing-driven fill with a modest setup slack threshold with -timing_preserve_setup_slack_threshold (ICC2), or list the few critical nets explicitly with -nets (ICC2), so fill keeps extra spacing from them. I would keep the threshold small, because too many protected nets leaves empty areas that fail minimum density. If density errors appear, signoff.create_metal_fill.fix_density_errors (ICC2) can fix them during the run. After fill I would extract with real fill and rerun timing on those nets.