How do sub-7nm FinFET pin-access design rules impact standard cell placement and legalization?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
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Short Answer
Below about 7nm, the lower metal layers (M1, M2, M3) are typically built with multi-patterning lithography (LELE or SADP) and strict unidirectional routing tracks — which means simply landing a via on a cell pin is no longer trivial the way it used to be. The core pin-access problem: connecting a via down to a tiny M1 pin stub has to simultaneously satisfy on-grid via center landing, minimum end-of-line enclosure on M1, and minimum cut-to-cut spacing across different lithography masks — three constraints that can easily conflict with each other on a dense cell.
Technical Explanation
- Below about 7nm, the lower metal layers (M1, M2, M3) are typically built with multi-patterning lithography (LELE or SADP) and strict unidirectional routing tracks — which means simply landing a via on a cell pin is no longer trivial the way it used to be.
- The core pin-access problem: connecting a via down to a tiny M1 pin stub has to simultaneously satisfy on-grid via center landing, minimum end-of-line enclosure on M1, and minimum cut-to-cut spacing across different lithography masks — three constraints that can easily conflict with each other on a dense cell.
- A very real, very common failure mode is "pin shadowing" — when two dense, multi-input standard cells get abutted, their M1 pins can land on the same routing track with less than the minimum tip-to-tip spacing, making it physically impossible for the router to drop a via on either pin without a DRC short.
- Modern placement tools address this with pin-access-aware legalization — before committing a cell's final site location, the legalizer actually checks local via accessibility, and if two cells would shadow each other, it inserts a small dummy diffusion filler gap between them rather than letting the collision happen.
- Foundries also provide explicit asymmetric cell placement spacing rules (
set_placement_spacing_labelin ICC2) that flatly prohibit certain cell-pair abutment combinations known to cause pin-access problems — this isn't a general DRC rule, it's a specific cell-to-cell table. - The practical takeaway: at these nodes, placement legality isn't just "do the cells overlap" — it now genuinely includes "can the router actually reach every pin," which means legalization has to reason about via accessibility, not just geometric non-overlap.
Common Mistake
The Trap: Disabling pin-access aware placement to achieve artificially higher placement density. The design will appear legal during placement but will generate tens of thousands of unroutable pin-access DRC shorts.
Follow-up Question & Model Response
"What is a placement spacing label in advanced FinFET nodes?"
Candidate Model Response: A placement spacing label is a foundry metadata tag assigned to complex cells that defines minimum site clearance requirements when placed next to cells with opposing spacing labels.
Practical Example
Configuring Pin-Access Aware Placement:
# Synopsys ICC2: Enable pin-access aware global placement & legalization
set_app_options -name place.coarse.pin_density_aware -value true
set_app_options -name place.legalize.enable_pin_accessibility -value true
# Audit pin access violations pre-route
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