How do you resolve severe standard cell placement congestion in narrow channels between hard macros?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Narrow corridors between adjacent SRAMs or IP blocks are the single most common source of unroutable placement layouts — the global placer naturally wants to pack logic there to minimize wirelength to nearby macro pins, without knowing the channel's metal tracks are already spoken for by macro power rings, PG straps, and wide data buses. Remedy 1 — partial placement blockages: cap placement density in the channel (say, 30-50%), which leaves the router room to use the rest of the channel's tracks for macro feedthroughs and bus routing while still allowing some minimal buffer placement.
Technical Explanation
- Narrow corridors between adjacent SRAMs or IP blocks are the single most common source of unroutable placement layouts — the global placer naturally wants to pack logic there to minimize wirelength to nearby macro pins, without knowing the channel's metal tracks are already spoken for by macro power rings, PG straps, and wide data buses.
- Remedy 1 — partial placement blockages: cap placement density in the channel (say, 30-50%), which leaves the router room to use the rest of the channel's tracks for macro feedthroughs and bus routing while still allowing some minimal buffer placement.
- Remedy 2 — macro keepout halos: apply a placement halo around each macro's perimeter so standard-cell logic can't choke off the macro's own pin-escape corridors, which is often what actually causes the worst local congestion.
- Remedy 3 — soft blockages that permit only buffers: forbid ordinary standard-cell logic in the channel during initial placement but still allow timing-critical buffers to land there during
place_opt, since some buffering is genuinely useful in that corridor. - Remedy 4 — if none of the above is enough because total track demand simply exceeds the channel's physical capacity, that's a floorplan-level problem, not a placement-tuning one — widening the channel is the only real fix at that point.
Common Mistake
The Trap: Applying a 100% hard blockage inside macro channels. This prevents the tool from inserting necessary pipeline repeaters on long inter-macro nets, destroying timing closure.
Follow-up Question & Model Response
"Why are soft blockages preferred over hard blockages inside macro channels?"
Candidate Model Response: Soft blockages prevent dense combinational logic from clustering in the channel during initial placement, while allowing place_opt to insert critical timing repeaters.
Practical Example
Applying Macro Channel Blockages:
# Synopsys ICC2: Create a 40% partial placement blockage in macro channel
create_placement_blockage -type partial -blocked_percentage 60 -boundary {{200 150} {240 500}}
# Create soft blockage allowing buffer-only insertion
create_placement_blockage -type soft -boundary {{240 150} {280 500}}Physical Design & Planning Handbook
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