What are Tie Cells (TIEHI / TIELO), and why are direct connections to VDD/VSS prohibited?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Tie cells give a gate a clean, high-impedance logic-1 or logic-0 reference instead of letting a designer wire an input straight to the VDD or VSS rail — that direct wiring is actually dangerous, not just sloppy. Power rails aren't perfectly quiet: switching transients create inductive voltage spikes (L·di/dt), and a direct tie exposes the transistor's ultra-thin gate oxide to those spikes, which can literally punch a hole through it.
Technical Explanation
- Tie cells give a gate a clean, high-impedance logic-1 or logic-0 reference instead of letting a designer wire an input straight to the VDD or VSS rail — that direct wiring is actually dangerous, not just sloppy.
- Power rails aren't perfectly quiet: switching transients create inductive voltage spikes (L·di/dt), and a direct tie exposes the transistor's ultra-thin gate oxide to those spikes, which can literally punch a hole through it.
- There's a second, earlier hazard too — during wafer fabrication, plasma etching charges long metal rails, and a direct tie funnels that stray charge straight into the gate before the chip is even packaged (the antenna problem).
- Internally a TIEHI cell is a current-limiting saturated MOS "resistor" that pulls the output to VDD gently and with high impedance, which is why it can only safely drive a limited number of loads — typically 8 to 16 gate inputs — before it needs to be replicated.
Common Mistake
The Trap: Letting a single TIEHI cell drive 2,000 unused bus pins across the entire chip. This causes catastrophic max-capacitance DRC violations and creates a massive high-fanout net.
Follow-up Question & Model Response
"How do you verify that zero gates in your design are tied directly to VDD/VSS rails?"
Candidate Model Response: Run check_tie_cells or inspect LVS netlist reports to confirm all static 1'b0 and 1'b1 inputs terminate on approved TIEHI/TIELO cell output pins.
Practical Example
Tie Cell Insertion Commands:
# Synopsys ICC2: Connect tie cells with a maximum fanout limit of 8
connect_tie_cells \
-objects [get_pins -filter "is_tied_to_power == true || is_tied_to_ground == true"] \
-tie_high_lib_cell [get_lib_cells */TIEHI*] \
-tie_low_lib_cell [get_lib_cells */TIELO*] \
-max_fanout 8Physical Design & Planning Handbook
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