What does a gate-level netlist contain?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
A gate-level netlist describes the circuit as instances of cells or modules connected by nets. It captures logical connectivity, rather than the final physical locations and wire shapes.
Technical Explanation
Think of a cell as a component, a pin as its terminal, a net as a connection, and an instance as one particular use of that component. In a Verilog netlist, module declarations describe the hierarchy, ports define interfaces, wire declarations name connections, and instantiations connect library pins to those wires. A library cell such as an inverter can appear hundreds of times under different instance names. The implementation handoff is normally technology-mapped: generic logic has been mapped to cells supported by the selected libraries. It may already contain scan flops, clock-gating cells, tie cells, or low-power cells, depending on the upstream flow. Do not infer the insertion stage from the filename. Check the synthesis and DFT handoff reports. Before trusting it, confirm the top module, hierarchy, port directions and widths, expected cell counts, and the existence of models for referenced cells. Investigate unintended undriven nets and multiple drivers. An intentionally black-boxed macro is acceptable only when its implementation interface and required models are supplied through the approved methodology.
Common Mistake
Treating a net name as a cell name, or assuming that a connected netlist proves timing correctness.
Follow-up Question & Model Response
Can placement change the netlist? Optimization can resize or insert cells and alter connectivity while preserving the required logical behavior; equivalence checking validates that behavior.
Practical Example
INV_X1 u_inv (.A(data_in), .Y(n1)); names INV_X1 as the cell type, u_inv as the instance, A and Y as library pins, and data_in and n1 as nets. It says nothing about u_inv's final x/y coordinates.
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