IntermediateQuestion 7 of 20Source PDF page 41

How do you constrain a DDR-style interface where data needs both -clock and -clock_fall input delays?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

Explanation

A DDR (double data rate) interface can launch or capture data on both clock edges, so a single input delay referencing only the rising edge isn't enough. -clock_fall tells the constraint to reference the falling edge instead, and both the rising and falling constraints need to coexist rather than overwrite one another.

Timing-path Walkthrough

You would apply set_input_delay referencing -clock clk normally for the rising-edge case (with its own max/min values), and a second set_input_delay referencing -clock clk clock_fall for the falling-edge case (with its own max/min values). Because both specs land on the same port, -add_delay is required so they accumulate as separate valid constraints instead of the falling-edge spec silently overwriting the rising-edge one.

Command

set_input_delay ... -clock clk [-clock_fall] [-max|-min] ... -add_delay

Switch-by-switch

-clock_fall: references the falling edge instead of the default rising edge, used when external logic launches or captures on the falling edge. -max/-min: qualify the value as setup-relevant or hold-relevant. -add_delay: makes multiple input_delay specifications on the same port accumulate as separate valid constraints instead of a later one overwriting an earlier one.

Expected Report Behavior

report_timing should show two independent sets of input-delay-driven paths at the port — one referencing the clock's rising edge, one referencing its falling edge — rather than only one surviving.

Mentor Note — Common Mistake

Applying a second set_input_delay on the same DDR port without -add_delay, so the falling-edge constraint silently overwrites the rising-edge one (or vice versa), leaving one edge unconstrained.

How To Debug

Inspect the constraints on the port (or check_timing output for no_input_delay warnings) to confirm both rising and falling edge input delays are simultaneously present rather than one having overwritten the other.

Visual explanationSTA context: How do you constrain a DDR-style interface where data needs both -clock…
STA context: How do you constrain a DDR-style interface where data needs both -clock…A three-step concept map summarizes the focus, core answer, and practical verification for How do you constrain a DDR-style interface where data needs both -clock and -clock_fall input delays?Question focusHow do you constrain aDDR-style interfacewhere data needs both-clock…Core answerA DDR (double data rate)interface can launch orcapture data on…Verify in practiceset_input_delay ...-clock clk [-clock_fall][-max|-min] ...-add_delayUnderstand → explain the mechanism → verify the assumptions

Continue learning free

Get a practical low-power chapter

Receive the existing “Low Power and Multivoltage Fundamentals” PDF chapter and its download link by email.

Continue practising

Related STA questions

IntermediateHow do you define a generated clock correctly, and what goes wrong if you use create_clock instead on a divided clock?IntermediateWhat's the difference between clock source latency and clock network latency, and why model them separately before CTS?IntermediateWhat's the difference between clock uncertainty and clock jitter?IntermediateWhat is clock propagation, and what does set_propagated_clock actually change?