What's the difference between clock source latency and clock network latency, and why model them separately before CTS?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Explanation
Source latency models the delay from the clock's true origin (such as an off-chip source or a PLL) to the point where the clock is defined in the design. Network latency models the estimated on-chip delay through the clock tree itself. Both are set with set_clock_latency as placeholders before a real clock tree physically exists.
Timing-path Walkthrough
Before CTS, there is no real tree to compute insertion delay from, so the tool needs an estimate to keep timing analysis meaningful. set_clock_latency lets an engineer supply an estimated source and/or network latency so setup and hold checks have plausible arrival-time numbers to work with, rather than defaulting to zero delay everywhere.
Command
set_clock_latencySwitch-by-switch
Specifies an estimated clock insertion delay, split into source latency (delay from the true
clock origin, e.g. off-chip or PLL, to the clock definition point) and/or network latency (the
estimated on-chip tree delay).Expected Report Behavior
Clock path sections of report_timing show the estimated latency values in place of real tree delay until CTS completes and set_propagated_clock takes over.
Mentor Note — Common Mistake
Forgetting to update or remove estimated set_clock_latency values after CTS, so stale pre-layout estimates linger alongside or instead of the real propagated clock.
How To Debug
Check whether clock path entries reflect the estimated latency figures supplied via set_clock_latency during pre-CTS stages, and confirm they are superseded once set_propagated_clock is applied.
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