IntermediateQuestion 52 of 112Source: Synopsys PrimeTime User Guide: Input Delays

How do you model asymmetric I/O timing with separate -max and -min values on set_input_delay?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

An external driver's arrival time at an input port is not always symmetric, so set_input_delay accepts separate -max and -min values instead of one flat number. The -max value feeds the setup check, since setup cares about the slowest realistic arrival, and -min feeds the hold check, since hold cares about the fastest realistic arrival.

Technical Reference DiagramHow do you model asymmetric I/O timing with separate -max and -min values on set_input_delay?
An external driver chip connected to input port DATA_IN, with two labeled delay arrows, a 2.0ns minimum feeding the hold check and a 4.5ns maximum feeding the setup check, both relative to the same clock edge.

Technical Explanation

An input port's arrival time is not always symmetric — the fastest and slowest paths from an external driver can differ enough that one flat number would misrepresent one of the two checks.

  • set_input_delay (SDC) accepts separate -max and -min values. -max feeds the setup check, since setup cares about the slowest realistic arrival; -min feeds the hold check, since hold cares about the fastest realistic arrival.
  • Without -max/-min, a single value applies to both checks. That is fine when the external driver's delay is well characterized and roughly symmetric, but it understates real variation when the driver's fast and slow corners are far apart.
  • The two values usually come from the driving chip's datasheet or characterization, listing a minimum and maximum output delay relative to the shared clock edge — the same way a cell's own datasheet lists best-case and worst-case delay.
  • A wide max/min spread usually means a longer, less controlled off-chip path — a driver several inches away on a noisy board typically has more delay variation than one sitting right next to the receiving pin.
  • Getting max and min backwards silently inverts the margin. Since -max feeds setup and -min feeds hold, swapping them makes the setup check artificially lenient and the hold check artificially strict, or the reverse, without any error from the tool.
  • Why it matters: using one flat input delay value when the real driver has a wide max/min spread can pass a setup or hold check that a real, worst-case external signal would actually violate.

Common Mistake

The Trap: entering a single flat input delay value for an external driver whose datasheet actually lists a wide range between minimum and maximum output delay.

  • Using the datasheet's typical or maximum value for both checks can make the hold check unrealistically strict, since hold actually needs the driver's fastest-case delay, not its slowest.
  • Swapping -max and -min by mistake is the more dangerous version of this error, since it silently loosens the check that should be tight and tightens the one that should be loose, with no warning from the tool.

Follow-up Question & Model Response

A driving chip's datasheet lists output delay as 2.0ns minimum and 4.5ns maximum relative to the shared clock edge. How would you constrain the receiving input port?

Candidate Model Response: I would apply set_input_delay -clock CLK -max 4.5 [get_ports DATA_IN] and set_input_delay -clock CLK -min 2.0 [get_ports DATA_IN] (SDC), using the datasheet's slowest value for -max and fastest value for -min. That way the setup check, which uses -max, is tested against the worst-case slow arrival, while the hold check, which uses -min, is tested against the worst-case fast arrival. Using a single flat value, like the 4.5ns maximum for both, would make the hold check unrealistically strict and could flag a violation that the real 2.0ns fast-case arrival would never actually cause.

Practical Example

A companion chip drives DATA_IN with a datasheet-specified output delay range of 2.0ns to 4.5ns relative to the shared 100MHz clock. The team applies set_input_delay -clock CLK -max 4.5 [get_ports DATA_IN] and set_input_delay -clock CLK -min 2.0 [get_ports DATA_IN] (SDC). The setup check on the receiving flop's first-stage logic uses the 4.5ns value and passes with 800ps of margin, while the hold check uses the 2.0ns value and separately passes with 300ps of margin — two distinct checks, each against the correct end of the driver's real timing range.

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