IntermediateQuestion 53 of 112Source: Synopsys PrimeTime User Guide: Output Delays

What does set_output_delay actually constrain, and how is the available time computed?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

set_output_delay reserves part of the clock period for an external device's own setup and hold requirements after your output port changes, so the internal logic only gets the remaining part of the period to produce that signal. A larger output delay value leaves less time for internal logic, since more of the period is set aside for the receiving device.

Technical Reference DiagramWhat does set_output_delay actually constrain, and how is the available time computed?
A 10ns clock period bar split into a 7ns internal-logic segment and a 3ns reserved segment labeled as the receiving memory device's own setup requirement, feeding an arrow into an external memory chip.

Technical Explanation

set_output_delay describes the time an outgoing signal is allowed to spend traveling before an external device needs it to be stable.

  • set_output_delay 3 -clock CLK [get_ports OUT1] (SDC) sets the required time between the output port and the external device's own capturing clock edge. The -clock argument is which edge the external device actually uses to sample the signal, not necessarily the same edge that launched the data inside the chip.
  • The available time for the internal path is the clock period minus the output delay. If the external device needs the output delay to be, say, 3ns before its next clock edge, the internal logic only gets the remaining part of the period to produce that signal.
  • A larger output delay value means less time for internal logic, since more of the period is reserved for the external device's own setup requirement — it works the opposite way from source-side timing, where more delay is often a comfort, not a cost.
  • -max and -min split the same way as set_input_delay (SDC). -max sets the value used by the internal setup check on the output path, and -min sets the value used by the internal hold check, matching the external device's own worst-case fast and slow requirements.
  • The value should come from the receiving device's actual setup and hold requirements, the same way an internal flip-flop's own library timing arcs define its setup and hold windows — a receiving memory or ASIC's datasheet plays that same role here.
  • Why it matters: an output delay set too small looks like extra internal timing margin, but it actually understates what the external device really needs, which can pass internal STA cleanly while still failing at the board level.

Common Mistake

The Trap: treating a small output delay value as generous internal margin, without checking whether it actually reflects the receiving device's real setup and hold requirements.

  • A designer entering a conveniently small value to ease internal closure is really understating the external need, not creating real margin.
  • This kind of mistake passes clean in internal STA and only shows up as a board-level or system-level failure, since the internal analysis has no way to know the external requirement was understated.

Follow-up Question & Model Response

A receiving memory device needs 3ns of setup time before its own clock edge. Your chip's clock period is 10ns. How much time does your internal logic actually have to produce that output?

Candidate Model Response: With set_output_delay 3 -clock CLK [get_ports DATA_OUT] (SDC), internal logic effectively has the 10ns period minus 3ns reserved for the memory's setup requirement — about 7ns to produce a stable output value. If the internal path only needs 5ns, there is 2ns of real margin; if I instead entered a smaller, unjustified output delay value like 1ns to make internal timing look easier, the chip would report 9ns available internally, but the memory would still only get roughly 1ns of real setup time in practice, well short of its actual 3ns requirement.

Practical Example

A chip drives a DDR-style memory's DATA_OUT port at a 10ns clock period, and the memory's datasheet specifies a 3ns setup requirement before its own capturing edge. The team applies set_output_delay 3 -clock CLK [get_ports DATA_OUT] (SDC), leaving 7ns for the internal logic path from the launching flop to the output port. report_timing -to [get_ports DATA_OUT] (PT) then correctly shows the internal path being checked against a 7ns budget rather than the full 10ns, matching what the memory actually requires.

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