How do you tell PrimeTime that two clocks are asynchronous with set_clock_groups?

Short Answer

set_clock_groups -asynchronous (SDC) tells the tool that the listed groups of clocks have no fixed timing relationship to each other at all, so it should not build a setup or hold check across any path between them. Paths within each group are still checked normally.

Technical Explanation

Some clocks genuinely never share a stable phase relationship, and the SDC file has to say so explicitly.

• What the tool assumes by default: without a set_clock_groups statement, the tool will still try to build a setup and hold relationship between any two clocks that share a path, even if those clocks come from unrelated crystal oscillators.
• What -asynchronous changes: listing -group {CLK1} -group {CLK2} with the -asynchronous option (SDC) removes every cross-clock path between those two groups from setup and hold analysis, since no fixed edge relationship exists to check.
• It does not remove the paths within a group: clocks placed in the same group are still fully checked against each other and against themselves — the command only affects paths crossing between different groups.
• A related option, -logically_exclusive: this marks clocks that can never be active at the same time at all, such as two clock sources feeding the same mux where only one path is ever selected, rather than clocks that run simultaneously but with no fixed phase.
• Why this is not the same as a false path: set_false_path (SDC) removes one specific logic path from checking; set_clock_groups -asynchronous (SDC) removes every path between two entire clock domains in one statement, which is the right tool when the relationship itself, not just one path, is genuinely undefined.

Follow-up Question & Model Response

If two asynchronous clocks are grouped, does the crossing signal need anything else in the design itself? Candidate Model Response: Yes — set_clock_groups -asynchronous (SDC) only tells the static timing tool to stop checking a meaningless setup/hold relationship across that boundary. It does nothing to make the actual signal crossing safe in silicon. The design still needs real synchronization hardware, typically a chain of two or more flip-flops, so a signal changing near a capturing clock edge cannot cause the receiving flop to enter an unpredictable, unresolved state known as metastability.