How many clocks can one SDC file define, and do they need the same period?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
An SDC file can define as many clocks as the design has clock sources or generated-clock points — there is no fixed limit. Each clock gets its own independent period, waveform, and name, so none of them are required to match any other clock's period.
Technical Explanation
Each create_clock (SDC) statement stands entirely on its own.
- One statement per clock source: every distinct clock port or internal point that genuinely generates a clock edge gets its own
create_clockorcreate_generated_clock(SDC) call, so a design with five real clock sources has five statements. - Nothing forces a common period: the period argument on each
create_clock(SDC) call is independent — a 3ns clock and a 20ns clock can both exist in the same SDC file with no conflict. - Names must be unique: the
-namegiven to each clock (or the port name, if-nameis left out) is how every other command refers back to it, so two clocks cannot share a name even if their periods happen to match. - The tool builds a separate schedule per clock: internally, each clock gets its own list of edge times going forward in time, and the tool only compares two clocks' edges directly when a path actually crosses between them.
- More clocks means more scenarios to check, not more complexity per clock: each additional clock adds paths the tool must analyze, but does not change how any single clock's own period or waveform is calculated.
Common Mistake
The Trap: assuming every clock in a design should be given the same period for simplicity, or matched up "just in case."
- A designer picks one nominal period and applies it to every clock definition, even clocks that drive genuinely different, slower interfaces.
- This over-constrains the slower domains for no reason, forcing extra synthesis and place-and-route effort to meet a speed the real interface never needed.
Follow-up Question & Model Response
If two clocks in the same SDC file happen to have the exact same period, does the tool treat them as one clock domain? Candidate Model Response: No — the tool only cares about the name and definition actually used, not a numeric coincidence. Two clocks with identical periods but different names, and no generated-clock relationship linking them, are still treated as fully separate domains with no fixed phase relationship. A path crossing between them is still a clock domain crossing and needs the same synchronization and exception handling as any other pair of unrelated clocks, regardless of the matching period.
Practical Example
One SDC file defines CLK_CPU at a 1.5ns period, CLK_MEM at a 2ns period, and CLK_UART at a 651ns period for a 1.536MHz interface — three create_clock (SDC) statements, three different periods, none required to relate to the others.
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