BeginnerQuestion 51 of 95Source: Synopsys PrimeTime User Guide: Specifying Clocks

What does set_clock_transition do, and how is it different from set_clock_uncertainty?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

set_clock_transition (SDC) tells the tool how slow the clock edge itself is — its rise or fall time — when the clock network is still ideal and has no real buffers to measure that from. set_clock_uncertainty (SDC) is a completely different number: extra margin subtracted from the setup or hold check to cover skew and jitter.

A clock waveform edge labelled with a transition time value next to a separate required-time arrow shortened by an uncertainty margin — Technical Reference DiagramWhat does set_clock_transition do, and how is it different from set_clock_uncertainty?

Technical Explanation

Both commands attach a number to a clock, but they describe different physical things.

What clock transition means: it is the edge speed of the clock waveform itself — how many picoseconds it takes to swing from low to high — the same kind of measurement set_input_transition (SDC) gives a data pin.
Why an ideal clock needs it typed in: before the clock tree is built, the clock has no real buffers to derive a transition time from, so set_clock_transition (SDC) supplies a stand-in number so downstream cell delays can still be calculated realistically.
What clock uncertainty means instead: it is a margin, in time, added to the required time on the capture side to represent skew and jitter the tool cannot compute exactly, not a property of the waveform's shape.
They affect the report in different ways: clock transition changes how fast downstream cells are assumed to switch, which changes delay calculation; clock uncertainty changes the required time directly, tightening slack without touching any delay number.
Once real clock buffers exist, transition is no longer typed in: after set_propagated_clock (SDC) is applied and the clock tree is built, the tool measures real transition times from the actual buffers instead of using the value from set_clock_transition.

Common Mistake

The Trap: confusing the two commands and using set_clock_transition to try to add setup margin.

A designer wants to add pessimism for skew and jitter but sets a large set_clock_transition value instead of set_clock_uncertainty (SDC), assuming a bigger transition number means more margin.
This distorts every downstream cell's delay calculation instead of adding clean margin, producing delay numbers that no longer match how the real clock tree will behave.

Follow-up Question & Model Response

Once the clock is propagated, does set_clock_transition still do anything? Candidate Model Response: Generally no — once set_propagated_clock (SDC) is applied and a real clock tree with actual buffers exists, the tool computes each buffer's real output transition from the library data, the same way it does for any other cell. The typed-in set_clock_transition value was only ever a placeholder for the pre-propagation, ideal-clock stage, when no real buffer existed yet to measure a transition time from.

Practical Example

Before clock tree synthesis, a designer sets set_clock_transition 0.15 [get_clocks CLK_CORE] (SDC) so early setup checks use a realistic 150ps clock edge instead of an instantaneous zero-time edge, which would otherwise make every downstream cell's delay look artificially fast.

Complete STA Handbook