Why does create_clock need a period value, and what happens if you pick the wrong one?

Short Answer

The period is what lets the tool compute a required time at all — every setup check measures arrival time against one clock cycle length, so create_clock (SDC) cannot build a usable clock without it. Picking a period looser than the real target hides real violations; picking one tighter wastes design effort chasing margin nobody needed.

Technical Explanation

The period is not a label, it is the number every downstream setup and hold check is built from.

• What the period drives directly: the setup check's required time comes from adding one clock period to the launch edge, so a wrong period shifts every required time in that domain by the same wrong amount.
• Too loose hides real problems: a period set longer than the chip must actually achieve makes every path in that domain look like it has extra slack it will not really have once the chip runs at its intended speed.
• Too tight wastes real effort: a period set shorter than necessary forces synthesis and place-and-route to spend area, power, and schedule chasing margin that the actual product specification never required.
• The period should come from the real target, not a guess: the number belongs to the chip's specification — a target clock frequency from the datasheet or system architecture — converted into the library's time unit, not picked casually.
• A generated clock inherits the risk: because create_generated_clock (SDC) derives its own period mathematically from the source clock's period, an incorrect source period propagates the same error into every generated clock built from it.

Follow-up Question & Model Response

If the real target frequency changes late in the project, is updating create_clock's period enough by itself? Candidate Model Response: Updating the period is necessary but rarely sufficient by itself. Every setup and hold check in that domain, and every generated clock derived from it, is recomputed against the new number, so previously passing paths can immediately show new violations. The design usually needs another pass through synthesis or place-and-route optimization to actually meet the tighter number in real cells and wires, not just in the constraint file.