What actually happens, step by step, during a full setup check on a launch-to-capture path?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Explanation
A setup check makes sure data launched by one clock edge arrives at the capture flop with enough margin before the next active edge. The tool adds up everything that delays the data (clock-to-Q, logic delay), then compares it against the capture edge position adjusted for skew and uncertainty.
Timing-path Walkthrough
Using the worked numbers: Tcq=0.12, Tlogic,max=1.45, Tsu=0.08, uncertainty U=0.05, and skew S=+0.06. Plugging into the setup inequality gives a minimum period Tmin = 0.12+1.45+0.08+0.05−0.06 = 1.64 ns, which corresponds to an Fmax of roughly 610 MHz. If skew had instead been −0.06, the design would lose 120 ps of setup budget, raising Tmin to 1.76 ns.
Equation
L + Tcq + Tlogic,max ≤ C + T − Tsu − U ⇒ Tcq + Tlogic,max + Tsu + U
≤ T + SExpected Report Behavior
report_timing on this path shows data arrival time built from clock-to-Q plus cumulative logic delay, and a data required time derived from the period minus setup and uncertainty, adjusted by skew; the final slack line reflects the difference.
Mentor Note — Common Mistake
Assuming skew always helps setup — a positive S in this example reduces required-time pressure, but if the sign flips (skew works against you), the same design can suddenly fail setup at the same frequency.
How To Debug
Recompute the inequality by hand with the reported Tcq, Tlogic,max, Tsu, U, and S values to confirm the tool's slack number matches the arithmetic before chasing a fix.
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