What actually happens, step by step, during a full hold check on a launch-to-capture path?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Explanation
A hold check guards against data racing through too fast and corrupting the previous value still needed at the capture flop. It compares the fastest possible data arrival (using minimum delays) against the hold time requirement plus skew and hold uncertainty on the same edge.
Timing-path Walkthrough
With Tcq=0.12, Tlogic,min=0.09, hold time Th=0.05, hold uncertainty Uh=0.02, and skew S=+0.06: the sum Tcq+Tlogic,min = 0.12+0.09 = 0.21 is checked against Th+S+Uh = 0.05+0.06+0.02 = 0.13. Since 0.21 ≥ 0.13, the path passes with about 80 ps of margin. If skew had been −0.06 instead, the hold margin would improve to roughly +200 ps, since hold and setup respond oppositely to the sign of skew.
Equation
L + Tcq + Tlogic,min ≥ C + Th + Uh ⇒ Tcq + Tlogic,min ≥ Th + S + UhExpected Report Behavior
report_timing for a hold check shows the same-edge data arrival built from minimumdelay arcs, and a required time built from hold time, skew, and hold uncertainty; slack is arrival minus required.
Mentor Note — Common Mistake
Fixing a setup violation by adding delay can inadvertently create a hold violation on the same or adjacent path, since setup and hold pull in opposite directions on delay budget.
How To Debug
Check both the setup and hold slack after any delay change to the same path, since notes explicitly warn that fixing one can create the other.
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