BeginnerQuestion 48 of 95Source: Synopsys PrimeTime User Guide: Checking and Analyzing the Design

What happens in PrimeTime if you forget to define a clock on a clock port?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Without a create_clock (SDC) statement, the tool has no reason to treat that port as a clock at all — it times signals through it as ordinary combinational logic, and every flip-flop it should be clocking shows up as having no clock.

Technical Reference DiagramWhat happens in PrimeTime if you forget to define a clock on a clock port?
A clock port feeding several flip-flop clock pins, with the port marked as undefined and each flip-flop labelled no clock

Technical Explanation

The tool does not guess that a pin named CLK is special.

  • No automatic detection: the tool only knows a pin is a clock because a create_clock (SDC) statement names it — a port called CLK with nothing defined on it is treated as a plain data signal.
  • What that does to downstream flip-flops: every register whose clock pin traces back to that undefined port has, from the tool's point of view, no clock at all, so no setup or hold check can be built for it.
  • The signal still propagates as data: the tool will still compute an arrival time through the clock network as if it were logic, which produces a meaningless data-style delay number instead of a clock edge.
  • check_timing (PT) catches it: running check_timing reports "there are N register clock pins with no clock" as a warning during the no_clock check, which is the fastest way to catch a missing create_clock.
  • Every downstream constraint depends on it existing first: set_clock_uncertainty, set_clock_latency, and set_propagated_clock (all SDC) all reference a clock by name, so none of them can even be written correctly until the clock itself is defined.

Common Mistake

The Trap: assuming a missing clock definition will show up as an obvious setup or hold failure.

  • A designer expects that if create_clock were forgotten, the report would be full of huge violations that are easy to spot.
  • Instead, the affected registers simply disappear from setup and hold reporting entirely — no violation, no warning in report_timing, and the omission survives until someone runs check_timing (PT) and reads its no_clock warning.

Follow-up Question & Model Response

Why doesn't report_timing warn about the missing clock the way check_timing does? Candidate Model Response: report_timing (PT) only reports on paths it can actually build, and a register with no clock at its clock pin has no valid startpoint or endpoint for a clocked check, so there is no path to print in the first place. check_timing (PT) exists specifically to look for structural constraint gaps like this one, scanning every register's clock pin rather than waiting for a path to be requested. That is why running check_timing before trusting any report_timing output is standard practice.

Practical Example

An SDC file defines CLK_CORE and CLK_IO but a third clock port, CLK_DEBUG, is left out by mistake. check_timing (PT) reports "Warning: There are 12 register clock pins with no clock," pointing to every flip-flop on the debug domain that report_timing had silently skipped.

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