What are the major input files STA needs to run (netlist, library, SDC, parasitics)?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
A standard timing run is fed by several key inputs together: the netlist (the actual gatelevel logic connections), the timing library (characterized cell delay/timing data, in Liberty format), the SDC file (the design's timing intent and constraints), and parasitic data such as SPEF (extracted or estimated wire resistance/capacitance), along with MMMC configuration for multiple corners/modes.
Example
Before trusting any of it, the flow involves netlist readiness and linking steps, plus running check_timing and check_design as sanity checks on the setup.
Why It Matters
Each input answers a different question the tool needs to know: the netlist says what's connected to what, the library says how each cell behaves electrically, the SDC says what the design is intended to do and what to check, and the parasitics say how the actual wires slow signals down. STA can only produce a trustworthy answer when all of these pieces are present and correctly linked together.
Mentor Note — Common Mistake
Don't assume having just the netlist and library is enough to start meaningful analysis. Missing or incomplete SDC constraints, or stale/wrong parasitic data, can each independently invalidate the whole report even if everything else looks fine.
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