What is clock latency, and what's the difference between source latency and network latency?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
Clock latency, also called insertion delay, is the absolute time it takes the clock to travel from its source to a flip-flop's clock pin; it splits into source latency, the delay from the clock's true origin to its definition point, and network latency, the estimated delay through the on-chip clock tree itself.
Example
A designer can use set_clock_latency to specify an estimated insertion delay — covering source and/or network latency — as a placeholder before a real clock tree exists, and later switch to set_propagated_clock once CTS has built the actual tree.
Why It Matters
If you forget set_propagated_clock after CTS, every flop still looks like the clock arrives at t=0 with zero skew, so hold checks become meaningless and can pass in the tool while failing in real silicon.
Command
set_clock_latency (estimated insertion delay before a real tree exists);
set_propagated_clock (switches to real, built clock-tree timing after CTS)Mentor Note — Common Mistake
Leaving a design on estimated clock timing after the real clock tree has been built, instead of switching to propagated timing, which hides real skew and can let genuine hold violations slip through unnoticed.
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