What is clock reconvergence, and why does it matter for a hold check?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
Clock reconvergence happens when the launch and capture paths of a timing check share part of the same physical clock tree before splitting off to different flip-flops. Because that shared portion is the exact same silicon for both paths, on-chip variation applied to it should cancel out instead of being counted twice, once as an increase on one side and a decrease on the other. PrimeTime's clock reconvergence pessimism removal, CRPR, finds that shared portion and removes the extra, unrealistic pessimism it would otherwise add, which matters most for hold checks because hold margins are already small.
Technical Explanation
The shared part of a clock tree should not be derated in two opposite directions for the same check.
- Two flip-flops that trace their clock back through the same upstream buffers before branching share a "common clock path," even though their final few stages differ.
- Without CRPR, derating treats the launch and capture clock paths as if they were two unrelated pieces of silicon, even on the identical shared buffers.
- That double-counts variation on the shared segment: it derates the segment late for one path's role and early for the other, which cannot physically happen on one piece of silicon.
- CRPR calculates how much of the clock path is shared and subtracts the resulting excess pessimism;
report_timing(PT) can show the CRPR adjustment on the path detail line. - Hold margin is usually just tens of picoseconds, so even 20 or 30ps of spurious pessimism from an unremoved common clock path can turn a real pass into a false violation.
Common Mistake
The Trap: assuming CRPR removes all on-chip variation pessimism from a path, not just the pessimism from the shared clock segment.
- CRPR only cancels the double-counted variation on the common clock path; the diverging clock segments and the data path itself still get their normal derate.
- Treating a CRPR-adjusted slack as "fully de-pessimized" can lead a team to skip checking whether the remaining, still-derated portions of the path leave real margin.
Follow-up Question & Model Response
Does CRPR apply automatically, or does a design need to turn it on explicitly?
Candidate Model Response: CRPR is active by default in on-chip variation mode, since it is part of how the tool computes pessimism rather than a separate feature to enable. The tool walks back from both clock endpoints to find the last common clock point and removes the redundant derate up to that node. A design can restrict how far CRPR merges two clock paths using a merging threshold, controlling how similar two arrival times must be before the paths count as sharing a common point.
Practical Example
Two flops share the first 12 buffer stages of a 20-stage clock tree before splitting for the final 8 stages. Without CRPR, the shared stages get double-derated, adding roughly 35ps of unrealistic pessimism to a hold check. After CRPR removes that pessimism, the reported hold slack improves from -10ps, a false violation, to +25ps, a real pass.
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