What is combinational (logic) delay in a timing path?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
Combinational (logic) delay is the portion of a timing path's delay that comes from the chain of logic gates and interconnect between the launch point and the capture point, as opposed to the flip-flop's own internal delay.
Example
In a worked example, a path runs from FF1's Q output through gates U1, U2, and U3 (each contributing its own cell delay plus the net delay to the next gate) before reaching FF2's D input, with the individual increments summing to a total data arrival of 299 ps.
Why It Matters
Since combinational delay is usually the largest and most variable portion of a path's total delay, it's the primary thing physical design and synthesis try to optimize when fixing setup or hold violations.
Equation
data arrival = FF1/Q + U1/A(net) + U1/Z + U2/A(net) + U2/Z + U3/
A(net) + U3/Z + FF2/D(net) = 95+12+48+30+52+8+44+10 = 299 psMentor Note — Common Mistake
Forgetting that combinational delay alternates between cell delay (through each gate) and net delay (through each wire segment) — you must add up both types of increments along the whole path, not just the gate delays alone.
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