IntermediateQuestion 45 of 112

Why can a path have positive setup slack and negative hold slack at the same time?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Last updated: 28 Sept 2026

Short Answer

Setup and hold are two separate checks on the same path, comparing different arrival times against different requirements — one checks whether data arrives in time for the next clock edge, the other checks whether it stays stable long enough after the current edge. A path can easily pass one check with room to spare while failing the other, because nothing forces the two results to move together.

A single reg2reg path diagram with two parallel number lines below it, one showing +950ps setup slack and the other showing -25ps hold slack, both computed from the same 90ps data arrival time. — Technical Reference DiagramWhy can a path have positive setup slack and negative hold slack at the same time?

Technical Reference DiagramWhy can a path have positive setup slack and negative hold slack at the same time?

Technical Explanation

The two checks are independent, so a path's setup outcome tells you nothing about its hold outcome.

Setup checks the maximum path, hold checks the minimum path. Setup asks whether data arrives before the next clock edge; hold asks whether data stays stable long enough after the current edge. They use different arrival times and different requirements.
A slow, heavily buffered path is setup-friendly but hold-risky. Extra delay helps a path meet its setup deadline with room to spare, but that same delay can still be small compared to what hold needs if skew is unfavorable.
A very fast path is the opposite case. Minimal logic delay leaves generous setup slack, since there is plenty of time before the next edge, but a fast path is exactly the kind most likely to violate hold if there is any adverse skew at all.
The two checks do not trade off against each other on the same path. Fixing setup by adding delay can directly create or worsen a hold violation on the very same path, because the fix that helps one check works against the other.
This is why both must be checked and reported together, never one used as a proxy for the other — a report showing only setup slack, however good, says nothing about whether that same path holds.
Why it matters: a path with +300ps setup slack and -20ps hold slack is common in real designs, especially reg2reg paths with short combinational logic, and both numbers need their own fix.

Common Mistake

The Trap: seeing a large positive setup slack and assuming the path is broadly healthy, without checking hold separately.

A designer reviewing a summary report sorted by setup slack can miss that the very same path, or a nearby one sharing the same clock branch, is failing hold by a small margin.
Adding delay to "clean up" a setup number that was already comfortably positive can push a marginal hold path further into violation, since the fix for one check works against the other.

Follow-up Question & Model Response

If you needed to add a buffer to fix a hold violation on a path that already has +300ps of setup slack, would that setup number get worse?

Candidate Model Response: Yes, adding delay to fix hold necessarily increases the data arrival time, which eats directly into that setup slack. With 300ps of margin to start, a typical hold-fix buffer of a few tens of picoseconds is unlikely to cause a new setup violation, but I would still re-check the setup number after the fix rather than assume it stays comfortable. On a path with tighter setup margin to begin with, the same hold fix could push it into a setup violation, which is why ECO tools re-verify both checks after every change rather than only the one being targeted.

Practical Example

A reg2reg path in a 900MHz domain has almost no combinational logic — just a clock-to-Q delay of 90ps feeding directly into the next flop. Setup analysis at the 1.11ns period shows +950ps of slack, since the path is far shorter than the clock period allows. The same path's hold check, comparing that 90ps arrival against a 45ps hold-time requirement and 70ps of adverse skew from the capture flop's shorter clock branch, comes out to -25ps. The fix is a small delay buffer inserted in the data path, which trims the setup slack to roughly +920ps while bringing hold slack to +15ps — both checks now pass.

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