How do you model early and late clock source latency with set_clock_latency?

Short Answer

Source latency is the travel time from a clock's true origin — often an off-chip PLL — to the point in the design where you defined it with create_clock, and the tool cannot see that part of the path on its own. The set_clock_latency -source command with -early and -late lets you enter that travel time as a range, so setup and hold checks can each use whichever end of the range is worse for that specific check.

Technical Explanation

Clock latency is the time it takes the clock signal to travel from its true origin to where it enters the design being analyzed, and early/late values let you model that travel time as a range instead of one fixed number.

• Source latency covers the part of the clock path the tool cannot see. Anything before the clock reaches the port or pin named in create_clock (SDC) — an off-chip PLL, a board trace, a clock buffer chip — is outside the netlist, so the tool needs it typed in by hand.
• set_clock_latency -source (SDC) is how that number gets entered. Without it, the tool assumes the clock reaches its defined point with zero extra delay, which is rarely true once you count real board and PLL delay.
• -early and -late model the range that latency can actually take. A PLL's output delay is never a single fixed number in silicon — it varies with voltage, temperature, and process — so the tool lets you bound it instead of forcing one estimate.
• The setup check uses the late value and the hold check uses the early value, or the reverse, depending on which edge is being stressed — the tool picks whichever combination of early and late latency produces the worst-case result for each specific check, the same way it does for on-chip variation.
• Skipping the range and entering only one flat latency value hides exactly the variation the split is meant to model — a single number can't represent a PLL whose output delay swings by tens of picoseconds across corners.
• Why it matters: on a design with a real external clock source, an unrealistic single-value latency can make a marginal path look safely positive in one direction and quietly starve it in the other.

Follow-up Question & Model Response

Your board team says the PLL's output delay is 1.5ns typical but can vary by plus or minus 0.4ns across conditions. How would you enter that?

Candidate Model Response: I would set the early value to 1.1ns and the late value to 1.9ns using set_clock_latency -source -early 1.1 [get_clocks CLK] and set_clock_latency -source -late 1.9 [get_clocks CLK] (SDC), rather than entering 1.5ns once. That way the setup check, which wants the worst-case largest delay, picks up the 1.9ns late value, while the hold check, which wants the worst-case smallest delay, uses the 1.1ns early value. Using only 1.5ns for both would understate the setup risk and overstate the hold margin at the same time.