IntermediateQuestion 48 of 112Source: Synopsys PrimeTime User Guide: Specifying a Divide-by-2 Generated Clock

How do you define a basic divide-by-2 generated clock, and what does the tool assume about its duty cycle?

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By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A divide-by-2 clock comes from a flip-flop that toggles once every master-clock edge, and you define it with create_generated_clock -divide_by 2 -source, pointing -source at the pin where the master clock feeds the dividing flip-flop. Because the divider toggles symmetrically on every master edge, the tool assumes a clean 50% duty cycle by default, without needing a separate waveform.

Technical Reference DiagramHow do you define a basic divide-by-2 generated clock, and what does the tool assume about its duty cycle?
A flip-flop DIV1 with SYSCLK entering its clock pin and its Q output labeled DIV_CLK, showing a 1GHz master waveform above a derived 500MHz 50%-duty-cycle waveform below.

Technical Explanation

A divide-by-2 clock is the simplest generated clock: a flip-flop toggles on every edge of the master clock, so the output changes half as often.

  • create_generated_clock -divide_by 2 -source ... -name ... (SDC) is the standard way to define it. The -source option points at the pin where the master clock enters the dividing flip-flop, and -divide_by 2 tells the tool the output toggles once per two master edges.
  • The tool assumes a clean 50% duty cycle by default with -divide_by. Because the divider flip-flop toggles symmetrically off every master edge, the generated clock's high and low times come out equal, without needing a separate waveform statement.
  • PrimeTime does not look at the actual divider circuit to figure this out. It has no visibility into the flip-flop's internal logic, so create_generated_clock (SDC) is required even though the behavior seems obvious from the schematic — without it, the divided clock's output pin is just an unconstrained net.
  • The generated clock inherits the master's other properties automatically, including uncertainty and any explicit latency you set on the master, unless you override them directly on the generated clock's own object.
  • The relationship stays linked, not just copied once. If the master clock's period changes later — say a frequency scaling mode is added — the generated clock's period changes with it automatically, since it is derived, not a fixed independent value.
  • Why it matters: forgetting -source or pointing it at the wrong pin gives the tool no way to trace the divider relationship, so the generated clock's period would be wrong or the definition would fail outright.

Common Mistake

The Trap: pointing -source at the divider flip-flop's output pin instead of the pin where the master clock enters it.

  • The -source option identifies where the master clock reaches the generating logic, not where the generated clock leaves it — the generated clock's own point is given separately as the command's trailing pin argument.
  • Getting -source wrong usually does not produce an obvious error; it can silently derive the generated clock's timing from the wrong reference point, giving a period or phase that looks plausible but is not what the divider actually produces.

Follow-up Question & Model Response

If the master clock's period changes later in a low-power mode, does the divided clock's period update automatically, or do you need a second definition?

Candidate Model Response: It updates automatically, because a generated clock defined with -divide_by is derived from the master clock's characteristics at the time of analysis, not fixed at the time you wrote the command. If the master clock period doubles in a low-power scenario using a separate create_clock definition or a different SDC file for that mode, the divided clock's period doubles with it without any change to the create_generated_clock line itself. The one thing to double check is that the -source pin and master clock reference are still valid and unambiguous in that mode, especially if multiple clocks could reach the same source pin.

Practical Example

A 1GHz master clock SYSCLK feeds flip-flop DIV1, whose Q output is a 500MHz divided clock DIV_CLK. The team defines create_generated_clock -name DIV_CLK -source [get_pins DIV1/CP] -divide_by 2 [get_pins DIV1/Q] (SDC). The tool derives a 2ns period, 50% duty cycle clock for DIV_CLK, with 1ns high and 1ns low, matching the flip-flop's toggle behavior exactly, with no separate waveform statement required.

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