ExpertQuestion 45 of 69Source: Synopsys PrimeTime User Guide: Specifying Pulse Clocks

How do you specify a pulse clock with create_generated_clock -edges, and why does the position of the repeated edge digit change what pulse gets modeled?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A pulse clock — a signal that produces a narrow high or low pulse from each edge of a source clock — is defined with create_generated_clock -edges {n1 n2 n3} (SDC), where the three numbers name which edges of the source clock trigger the pulse's rise, its peak, and its fall. Repeating one of those edge numbers is what tells the tool "this is a pulse," and which edge number is repeated, and where in the list it repeats, determines whether the pulse is active-high or active-low and whether it is triggered from the source's rising or falling edge.

Technical Reference DiagramHow do you specify a pulse clock with create_generated_clock -edges, and why does the position of the repeated edge digit change what pulse gets modeled?
Waveform showing CLK's rising edge (edge 1) triggering an active-high 400ps pulse on CLKP via create_generated_clock -edges {1 1 3}, with edge 3 closing the pulse

Technical Explanation

  • create_generated_clock -source [pin] -edges {n1 n2 n3} [pulse_pin] (SDC) defines a pulse clock at [pulse_pin] as a new clock domain, distinct from the source clock it derives from.
  • The three numbers in -edges are source-clock edge numbers, counted 1, 2, 3 in order of occurrence — edge 1 is the source's first rising edge, edge 2 its first falling edge, and so on.
  • Repeating an edge number in the list (for example {1 1 3}) is the signal to the tool that this is a pulse generator, not a normal divided or gated clock — a normal generated clock never repeats an edge number.
  • The position of the repeated digit sets the pulse polarity: repeating the first two entries ({1 1 3}) makes an active-high pulse, while repeating the last two ({1 3 3}) makes an active-low pulse.
  • Which edge number is repeated sets which source transition triggers the pulse: a repeated odd number (from a rising edge) triggers the pulse from the source's rising edge; a repeated even number triggers it from the falling edge.
  • An alternative, set_sense -type clock -pulse (SDC), specifies the same rise/fall sense on an existing clock downstream of a point, without creating a new clock domain — useful when the pulse is just a sense change rather than a separately-named clock.
  • What breaks: specifying the pulse using estimated waveform edge times instead of the repeated-digit convention makes the delay check between the source clock and the pulse clock imprecise, because the tool cannot tie the pulse's timing directly back to the exact source edge that produced it.

Common Mistake

The Trap: Defining a pulse clock by estimating its rise and fall times directly, as ordinary waveform edges, instead of using the repeated-digit -edges convention tied to the source clock's own edges.

  • The pulse clock's period and offset then have to be kept in sync by hand every time the source clock's period changes, since nothing ties the two together automatically.
  • A source clock period change that isn't mirrored in the pulse clock's waveform produces a pulse clock definition that no longer matches the real circuit, and the tool has no way to flag the mismatch on its own.

Follow-up Question & Model Response

"What's the difference between using create_generated_clock -edges for this pulse and just using set_sense -type clock?"

Candidate Model Response: create_generated_clock with a repeated-digit -edges list creates a genuinely new clock domain at the pulse point, which means paths launched or captured by that pulse get their own startpoint/endpoint identity in reports, useful when downstream logic really is clocked by the pulse. set_sense -type clock -pulse (SDC) instead just redefines the sense of the existing source clock at that point in the network — the pulse is reported as the same clock domain, only with a different rise/fall waveform downstream. Choose the generated-clock form when the pulse latches its own register bank and needs independent constraints; choose set_sense when the pulse is purely a local waveform shape change with no new domain to track.

Practical Example

A memory controller derives a write-enable pulse CLKP from CLK's rising edge through an AND gate and an inverter delay of 400 ps on a 2 ns period clock. The SDC defines it as create_generated_clock -name CLKP -source CLK -edges {1 1 3} [get_pins and2/z], marking edge 1 (CLK's rise) as triggering an active-high pulse, with edge 3 (CLK's next rise) closing it. report_clock_timing on CLKP then shows a 400 ps pulse width tied directly to CLK's period, so a later change to CLK's period automatically updates CLKP's timing without touching the SDC.

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