ExpertQuestion 46 of 69Source: Synopsys PrimeTime User Guide: Generated Clocks and Unexpanded Clock Diagnostics

Why must a cascaded chain of divide-by generated clocks name the previous generated clock as its master, instead of all pointing back at the original clock?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Each stage of a divider chain — divide-by-2, then divide-by-4, and so on — needs its -master_clock (SDC) reference to be the generated clock immediately upstream of it, not the original source clock, because the tool derives a generated clock's waveform by tracing the real logic between it and its named master. Naming the original clock as master for every stage asks the tool to trace through logic already assigned to a different clock domain, which it cannot do, and the result is an unexpanded generated clock that PrimeTime cannot time correctly.

Technical Reference DiagramWhy must a cascaded chain of divide-by generated clocks name the previous generated clock as its master, instead of all pointing back at the original clock?
Divider chain MCLK to MCLK_div2 (master_clock MCLK) to MCLK_div4 (master_clock MCLK_div2, correct) versus MCLK_div4 incorrectly set with master_clock MCLK, producing an unexpanded generated clock

Technical Explanation

  • A cascaded divider — one flop producing a divide-by-2 clock, feeding a second flop that produces a divide-by-4 clock from it — needs two separate create_generated_clock (SDC) commands, one per stage.
  • The second stage's command must set -master_clock to the first stage's generated clock name and -source to the first stage's actual output pin, so the tool traces only the logic between those two points.
  • If the second stage instead names the original source clock as its master, the tool has to explain the relationship between the original clock and the divide-by-4 output by tracing through the first flop — logic that already belongs to the divide-by-2 clock's own domain.
  • PrimeTime cannot perform valid timing analysis for a generated clock whose source network or master relationship cannot be traced unambiguously; the tool reports this as an unexpanded generated clock, with error or warning codes such as UITE-461 or PTE-021/022/023/025/103 depending on the exact cause.
  • Common causes of an unexpanded generated clock include no real physical path between the generated clock and its stated master, edges or sense that don't match the actual circuit between them, or an ambiguous source network — for example, a loop — between the generated clock and its master.
  • Each create_generated_clock in the chain also needs -add (SDC) when more than one generated clock is defined from related points on the same master lineage, so the tool keeps every stage as a distinct, coexisting clock rather than overwriting a previous definition.
  • What breaks: an unexpanded generated clock either reports spurious constraint violations at every path it launches or captures, or is silently excluded from certain checks, and the SDC error looks like a netlist problem when the real cause is the master-clock chain being defined incorrectly.

Common Mistake

The Trap: Writing every stage of a divider chain with -master_clock pointing back at the single original clock, on the assumption that "master" always means the ultimate source rather than the immediately preceding stage.

  • The first divide-by-2 stage works fine, because it genuinely is derived directly from the original clock, which makes the mistake easy to miss during review.
  • The second stage then produces an unexpanded generated clock, and the resulting error messages point at a source-network tracing failure that looks like a bug in the netlist rather than in the SDC.

Follow-up Question & Model Response

"If I already see an unexpanded-clock warning, how do I confirm it's actually a wrong master-clock chain and not a real netlist problem?"

Candidate Model Response: Start with report_clock_timing -type latency (PT) on the flagged generated clock; if the tool cannot compute its source latency at all, that confirms the tracing itself is failing, not just producing an unexpected number. Then check the -master_clock and -source arguments of every create_generated_clock command in the chain, confirming each stage after the first points at the immediately preceding generated clock's name and output pin, not the original clock. If the chain is correct and the warning persists, only then is it worth checking the netlist for an actual missing or looped physical path between the stages, since a correct SDC chain resolves the vast majority of these warnings on its own.

Practical Example

A clock divider produces MCLK_div2 from MCLK at register reg1, then MCLK_div4 from MCLK_div2 at register reg2. The correct SDC reads create_generated_clock -name MCLK_div2 -master_clock MCLK -add -divide_by 2 -source MCLKIN [get_pins reg1/Q] followed by create_generated_clock -name MCLK_div4 -master_clock MCLK_div2 -add -divide_by 2 -source reg1/Q [get_pins reg2/Q]. An engineer who instead wrote both commands with -master_clock MCLK saw MCLK_div4 reported as unexpanded with a tracing warning, because the tool could not reconcile a divide-by-4 relationship against a master clock two stages removed from the real intervening logic.

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