What is the difference between pre-layout and post-layout STA?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
Pre-layout STA runs before physical placement and routing exist, so it relies on estimated or wire-load-based parasitics as a stand-in for real wires. Post-layout (postroute) STA runs after the chip has actually been placed and routed, using parasitics extracted from the real routed geometry (via SPEF), which is much closer to how the silicon will actually behave.
Example
The flow moves through stages of increasing accuracy: RTL, then Synthesis (ideal clock, estimated wires), then Placement (ideal clock, virtual RC), then CTS (real clocks), then Routing (real RC), and finally Signoff using tools like PrimeTime/Tempus with SPEF, MMMC, signal integrity, and on-chip variation considered.
Why It Matters
Early in the flow, the physical wires simply don't exist yet, so STA has to estimate their parasitics, often using a wire-load model, which is a legacy statistical estimate based only on fanout count and no real placement information. Only after routing can extraction give you the true, physical RC values, which is why post-layout numbers are trusted far more for final signoff decisions.
Mentor Note — Common Mistake
Don't treat pre-layout timing numbers as final. They're built on estimated wireload data rather than real geometry, and can look quite different once actual placement and routing exist.
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