Place & Route (PnR) for VLSI Physical Design Mentor Guide, 60 questions
Global, track and detail routing, congestion, vias, antenna, crosstalk, NDRs, postroute optimization and routing signoff checks.
Routing turns every logical connection into real metal. Before this stage a net is only an estimate, a straight or Steiner line the tools use to guess wire length and delay. The router replaces that guess with wires on real layers, joined by vias, that obey every width and spacing rule in the technology file.
The block has to be routable and roughly timing-clean before the router touches it. That means power and ground already routed, clocks built and propagated, estimated congestion acceptable, estimated timing close to zero slack, no max capacitance or transition violations, and a clean `check_routability`. Zroute also needs every design rule defined in the technology file, because that is the only place it reads rules from.
Global routing decides which regions a net passes through; detail routing decides exactly which tracks, layers and vias it uses. Global routing works on a coarse grid of global routing cells (GCells) and never draws real geometry. Detail routing draws the actual metal on tracks and cleans up every design rule violation.
Zroute, the ICC2 router, has five engines: global routing, track assignment, detail routing, ECO routing and routing verification. The first three can be run one at a time with `route_global`, `route_track` and `route_detail`, or all together with `route_auto`. ECO routing and verification are only reached through their own task commands, `route_eco` and `check_routes`.
Run the steps separately when you want to look at the result of global routing before paying for detail routing. `route_auto` runs all three engines back to back, which is fine on a stable block. On a new or congested block, stopping after `route_global` lets you read the congestion map and fix a hot spot in minutes instead of discovering it hours later as thousands of DRCs.
A GCell (global routing cell, or GRC) is one tile of the coarse grid the global router works on. Its capacity is how many nets can cross it in one direction, which comes from how many tracks fit: the number of layers running that way times the cell size divided by the track pitch. The router compares demand against that capacity in every GCell to decide where congestion is.
Overflow is how many more nets want to cross a GCell edge than there are tracks to carry them. If 14 nets want to cross and only 11 tracks exist, the overflow is 3. `report_congestion` adds overflow up across layers, and it ignores underflow, so a spare layer does not hide a crowded one.
Each metal layer has a preferred direction, horizontal or vertical, and the router keeps most wires on that layer running that way. Adjacent layers alternate direction so a horizontal wire on one layer never blocks a vertical wire on the next; they cross using a via. Wrong-way segments are legal but expensive, because they block tracks that other nets need.
Tracks are the lines a gridded router places wires on, laid out at the layer pitch, which is minimum width plus minimum spacing. A wire drawn on a track automatically keeps legal spacing from wires on the neighbouring tracks. A pin that does not line up with the track grid forces the router to jog off-grid, and those connections produce DRCs that are very hard to clean up.
Min and max routing layers set the band of metal that signal nets are allowed to use. M1 is usually kept for standard cell pins and the top layers for power and top-level routing, so the block routes in the layers between. Set them with `set_ignored_layers` before placement, because RC estimation and congestion analysis use them as well as the router.
A via is the vertical connection between two metal layers: a small cut through the insulator, with metal enclosure around the cut on both the layer below and the layer above. Every layer change in a route needs one. Via count matters because each via adds resistance, often more than the wire around it, and each single-cut via is a yield and reliability risk.
A redundant via adds a second cut next to an existing single cut, so the connection survives if one cut fails. The two cuts also share current, which lowers via resistance and improves electromigration margin. Success is measured by the redundant via conversion rate, the percentage of single vias that were converted.
Track assignment takes each global route, which only says which GCells a net passes through, and places its long segments on real tracks. It does this across whole rows and columns of the block at once, so parallel nets are spread sensibly before detail routing starts. After it finishes, every net is drawn in metal, but there are still many violations near pins for detail routing to fix.
Search-and-repair is the part of detail routing that clears design rule violations. The router first connects every net, even if that leaves shorts and spacing errors. It then runs repeated iterations that search for violations, rip up the wires involved in a small area, and reroute them until the violations are gone or stop improving.
The ones you see most are different-net spacing, shorts, minimum area, minimum width and length, end-of-line spacing, via enclosure problems, and open nets. `check_routes` lists them by type and saves the DRCs to the `zroute.err` error data; open nets appear in its text report. Knowing which type dominates tells you where to look for the cause.
An open is a pin that is not connected to the rest of its net, so the signal never arrives. A short is two different nets touching in the layout, so the silicon merges signals that the netlist says are separate. Both are hard failures that must be zero at signoff, and neither shows up reliably in timing reports.
`check_routes` is the router's verification check: it looks for DRCs, open nets, antenna violations and voltage area violations on routed signal nets. `check_lvs` is a connectivity check across signal, clock and power and ground nets that looks for shorts, opens and floating shapes. They overlap on opens and shorts, but each covers things the other does not.
The antenna effect is damage to a transistor's gate oxide during manufacturing, not during operation. While the chip is being built layer by layer, a long wire connected only to a gate collects electrical charge from the plasma etch steps. With no driver connected yet to drain that charge away, it can discharge through the thin gate oxide and damage it permanently.
There are two main fixes: layer hopping and diode insertion. Layer hopping breaks a long wire with a short jump to another layer near the gate, so less metal is attached to the gate during the risky etch step; Zroute prefers this by default. Diode insertion adds a protection diode that gives the collected charge a safe path to the substrate.
Crosstalk is unwanted coupling between two wires that run next to each other. When one wire, the aggressor, switches quickly, the coupling capacitance between them pushes a small voltage onto its neighbour, the victim. If the victim is quiet, that shows up as a glitch; if the victim is also switching, it changes the victim's delay.
Shielding places power or ground wires on both sides of a sensitive net, usually a clock, so no switching signal runs directly next to it. That removes almost all coupling from neighbouring signals. The cost is routing tracks, since one net now takes about three, and extra sidewall capacitance to the shields, which slows the shielded net.
A non-default routing rule (NDR) is a stricter set of width and spacing rules, and optionally specific vias, that you assign to chosen nets instead of the technology defaults. It is typically used on clocks and other critical nets: a wider wire lowers resistance and extra spacing lowers coupling. Width rules in an NDR are hard constraints and apply to via enclosures too.
Clocks are routed first so they get clean routing resources, their NDRs and any shielding, before thousands of signal nets fill the tracks. CTS balanced the tree assuming certain wire lengths and layers; routing the clocks first keeps that intact. If signal nets went first, clocks would be forced into detours that change skew and latency.
A routing blockage is a region where routing is not allowed on the layers you name. Zroute treats it as a hard rule, so wires detour around it. You use one to keep routing off sensitive areas, away from macro pins or edges that cause DRCs, or to reserve space, and you add `-zero_spacing` when the goal is to keep vias out.
Parasitic extraction calculates the resistance and capacitance of every routed net from its real geometry. Those values, usually written as SPEF, feed timing and signal integrity analysis. Before routing they are estimates; after routing they come from actual wire length, width, layers, vias and neighbours, so they have to be recalculated.
Resistance grows with length and falls with width and thickness. Capacitance depends on how much surface faces other metal and how close it is: long, tall, closely spaced wires have the most. For routing decisions the practical rules are simple: wider wires lower resistance, more spacing lowers coupling, and fewer vias lower resistance further.
Before routing, net delays come from estimates: virtual routes or global routes and estimated parasitics. After routing, every net has its real length, layers and vias, and real neighbours that add coupling. Those differences change delay, and crosstalk appears for the first time, so slack moves even though no cell moved.
`route_opt` fixes timing and logical design rule violations after routing, using real parasitics. It extracts, updates timing, then optimizes setup, hold, area and logical DRCs such as transition and capacitance, typically by sizing and buffering cells. It then legalizes the changed cells and ECO routes to connect the changed nets and clear DRCs, which can also touch neighbouring wires.
Look at three things: wire length per layer, the split between horizontal and vertical wiring, and via statistics including the double via rate. `report_design -routing` gives shape counts, wire length and via statistics, and `report_wirelength` gives length per layer and direction. Together they tell you whether the router used layers sensibly and how much yield protection the vias have.
Connectivity has to be perfect: zero opens and zero shorts. DRC and antenna violations have to be zero or individually reviewed and accepted. Timing, transition, capacitance and signal integrity have to pass on routed parasitics in every active scenario, and the block has to be saved with the reports that prove it.
`check_routability` checks that every pin can actually be reached and that the routing setup is legal before any routing starts. By default it checks blocked standard cell ports, blocked macro and top-level ports, out-of-boundary pins, minimum grid, via definitions, via cut blockages and minimum width settings. The two defaults worth remembering are the search ranges: twice the layer pitch for standard cell pins and ten times the pitch for macro and top-level pins.
First find it and measure it: which GCells, which layers, which direction and by how much. Then work out why: too many pins in a small area, a narrow channel between macros, too much wrong-way demand, or tracks lost to blockages or PG. The fix depends on the cause, so the diagnosis is most of the work.
Routing guides steer Zroute in an area without forbidding routing outright. Use preferred-direction-only or switch-preferred-direction guides to control direction, max-patterns guides to limit non-preferred-direction edges, track utilization guides to control density, access preference guides to prioritize areas, and river routing guides for tight channels. Zroute honours them, but they are softer tools than blockages.
A routing corridor restricts specific nets to a region made of connected rectangles, optionally with a min and max layer per rectangle. Global routing treats it as a hard constraint, but track assignment and detail routing treat it as soft, so they may step slightly outside to fix a DRC. If a routing guide conflicts with a corridor, the corridor wins.
A hard layer constraint is never broken: the router will not use a layer outside it. A soft one can be broken at a cost if that helps routing. For net-specific constraints set with `set_routing_rule`, the default is min layer soft and max layer hard, and you can change either default or set the mode per constraint.
For most clock nets, a double-width, double-spacing NDR is the better trade. It lowers resistance, lowers sidewall capacitance and keeps neighbours away, without the capacitance shields add. Shielding is kept for the most sensitive clock nets, where you need the strongest isolation from coupling and can afford the tracks and the extra load.
Start with postroute insertion, which almost every block uses. If that reaches about 80% and you need more, move to concurrent soft-rule insertion, which reserves space for second cuts while routing. Only if you already reach about 90% and still need more should you use near-100% insertion, because higher rates make DRC convergence and runtime worse.
You route critical nets first so they get clean, direct paths on the layers you want before thousands of other nets fill the tracks. Clocks are the usual example, but timing-critical signals, buses and nets with special rules benefit too. In ICC2 you give the nets their rules, route them with `route_group -nets`, and can lock them so later routing does not touch them.
Accumulated modes are stricter than single-layer, because they count metal on the current layer plus every layer below it, while single-layer counts only the current layer. ICC2 has six antenna modes, combining how area is measured (surface or sidewall) with how layers are counted (single-layer, accumulated-ratio or accumulated-area). The foundry rule decides which mode you must use.
When the aggressor and victim switch at the same time, the coupling capacitance changes how much charge the victim's driver must move. If they switch in opposite directions, the victim sees roughly its own capacitance plus twice the coupling, so it slows down. If they switch the same way, it speeds up, so crosstalk can hurt setup on one path and hold on another.
Turn on signal integrity analysis in the timer before postroute optimization, so extraction keeps coupling capacitance and timing includes crosstalk delta delay. `route_opt` then fixes the paths that actually fail with crosstalk instead of the ones that only look bad without it. You then re-check timing and noise with SI still enabled.
Use ECO routing limited to the changed nets; for a small ECO that is `route_eco -reroute modified_nets_only`. It connects open nets first and then fixes DRCs in the ECO area, leaving everything else as it was. Remember that incremental detail routing does not fix opens, so after netlist changes `route_eco` is the right tool, not `route_detail -incremental`.
First look at the DRC count per iteration to confirm it has really stopped falling. Then group the violations by type and location, because the pattern tells you the cause: a cluster at pins points to pin access, a dense area points to local density, macro edges point to access or blockages, and NDR nets point to rules. Fix that cause and rerun; more iterations rarely help once the curve is flat.
Hard macros and IP are often reused from older designs, and at smaller nodes their pins can sit too close to the macro edge, to each other or to blockages for the router to reach cleanly. `derive_pin_access_routing_guides` fixes this by creating routing guides, metal blockages around the macro with cutouts at each pin, and via blockages on the adjacent via layers. The cutouts give every pin a clear, rule-legal path in.
RC corners describe how manufacturing variation in metal width and thickness changes wire resistance and capacitance. Because the same variation pushes resistance and capacitance in opposite directions, no single corner is worst for every path. Cworst maximizes capacitance, RCworst maximizes the resistance-capacitance product, and the best corners are their opposites, used mainly for hold.
SPEF (Standard Parasitic Exchange Format, IEEE 1481) holds the extracted resistance and capacitance of every net. It has a header with the design name and units, a ports section, and one `D_NET` block per net with its connections, capacitors and resistors, including coupling capacitors to other nets. Before trusting one, check its units, that it covers every net, and that it came from the netlist you are timing.
Routing changes both clock and data timing. A clock branch that picked up extra delay moves the capture edge later, and a data path sped up by same-direction crosstalk or a short route arrives earlier, so hold margin shrinks. Postroute hold is fixed by adding delay to the data path near the capturing flop, usually with delay cells or buffers, and then re-checking setup.
A dangling shape is a piece of wire attached to a net at one end that goes nowhere; a floating shape belongs to a net but touches nothing of it. Both are usually left behind by rerouting and ECOs, and they add capacitance and can cause DRCs. `remove_redundant_shapes` deletes them without changing connectivity, but it skips open nets and nets with DRCs, so you re-check afterwards.
Signals crossing between voltage areas must go through the right isolation cells or level shifters, and the router must not create physical paths that break the power intent. Voltage area rules control whether nets may pass through an area and whether buffers can be added there. Cells with secondary power pins, such as always-on buffers, also need those pins routed to the correct supply.
Electromigration is metal atoms being pushed along a wire by current over years of operation, which eventually forms voids that open the wire or pile-ups that short it. Black's equation says lifetime falls with the square of current density and falls quickly with temperature. In routing, current density is what you control, so high-current nets get wider wires and more vias.
Connectivity first, then DRCs, then timing with signal integrity included, then hold, and re-check DRC and antenna after every round of fixes. Opens and shorts make every other number meaningless. DRC fixes move wires and change parasitics, so timing fixed before DRCs is timing you will fix again.
Late in the flow, you decide which nets the router is allowed to move. In ICC2 the `physical_status` attribute on a net sets its rerouting mode: `locked` freezes it, `minor_change` allows only small changes, and `unrestricted` is the default. Combine that with ECO routing limited to modified nets, and clean routing stays as it was.
Use the Custom Router for nets that need geometry Zroute is not built to produce: shielded buses, differential pairs, matched-length groups, and variable-width or variable-spacing routes. Typical cases are DDR interfaces, analog-sensitive nets and critical clocks between blocks. It pre-routes those nets with `route_custom`, and ICC2 then finishes the rest of the design normally.
In the hybrid flow the Custom Router routes the trunks of special nets and deliberately leaves some or all pin connections unfinished, and Zroute completes them. The two routers connect to pins differently, so letting Zroute make the pin connections avoids inconsistencies and DRCs. The split is set with `custom.route.skip_connect_pin_type`.
Near-100% insertion treats redundant vias as hard design rules during routing, which costs runtime, sometimes a lot, and makes DRC convergence harder. It only works during initial routing, not ECO routing, and Zroute relaxes it automatically if DRCs will not converge. Timing is protected with the timing-preserve options on `add_redundant_vias`, but only at the very end, because using them early crushes the via rate.
At double-patterning nodes one metal layer is printed with two masks, so every shape and via gets a mask colour and same-mask shapes need more spacing than different-mask ones. Routing has to assign colours legally, usually automatically during detail routing. Cut metal shapes are used to separate line ends, and writing DEF or GDS needs specific options so masks and cuts carry through.
A critical area is where a random particle defect would break the circuit: a conductive particle between two wires causes a short, and a missing piece of metal in a narrow wire causes an open. `spread_wires` moves wires apart to reduce short risk, and `widen_wires` makes wires wider to reduce open risk. They compete for the same space, so you balance them and protect timing on critical nets.
Compare the same path in both tools and find the first stage where they differ, then check the settings that feed it: extraction engine and corner, signal integrity settings, derates and variation, pessimism removal, clock propagation, scenario setup and missing annotations. The goal is to make the two agree, then fix in whichever tool matches signoff. A difference is almost always a setup difference, not a bug.
In a power-gated domain you have to prove that everything that must stay alive still has power when the domain is off. That means always-on buffers and their secondary power pins routed to the always-on supply, the isolation enable and switch control nets routed correctly, and no signal from the switched domain reaching always-on logic without isolation. Standard DRC checks do not see any of this, so multivoltage checks are required.
Change as little geometry as possible and then re-check everything. Place new cells on spare cells or free sites near their connections, protect the clean nets you cannot afford to move, and ECO route only the modified nets. Then re-extract and rerun the full set of checks: DRC, LVS, antenna, and timing in every scenario.